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    Circuits having programmable impedance elements
    1.
    发明授权
    Circuits having programmable impedance elements 有权
    具有可编程阻抗元件的电路

    公开(公告)号：US08687403B1

    公开(公告)日：2014-04-01

    申请号：US13157713

    申请日：2011-06-10

    申请人： Narbeh Derhacobian ,  Shane Charles Hollmer ,  Ishai Naveh

    发明人： Narbeh Derhacobian ,  Shane Charles Hollmer ,  Ishai Naveh

    IPC分类号： G11C11/00

    CPC分类号： H01L45/085 ,  G11C11/005 ,  G11C13/0007 ,  G11C13/0011 ,  G11C14/0045 ,  G11C14/009

    摘要： An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.

    摘要翻译： 集成电路（IC）装置可以包括具有多个易失性存储器单元的第一部分; 以及第二部分，其通过数据传输路径耦合到所述第一部分，所述第二部分包括多个非易失性存储器单元，每个非易失性存储单元包括在不同电阻值之间不止一次可编程的至少一个电阻元件。 存储器件还可以包括可由存取双极结型晶体管（BJT）访问的可变阻抗元件，其中至少一部分由形成在衬底上的半导体层形成。 存储器件还可以包括多个存储器元件，每个存储器元件包括形成在第一和第二电极之间的电介质层，该电介质层包括具有小于二硫化锗中银的迁移率的可溶性金属的固体电解质。

    Charge injection
    2.
    发明授权
    Charge injection 有权
    电荷注入

    公开(公告)号：US06567303B1

    公开(公告)日：2003-05-20

    申请号：US10050483

    申请日：2002-01-16

    申请人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

    发明人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445

    摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

    摘要翻译： 提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。 因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    3.
    发明授权
    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
    使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间

    公开(公告)号：US06549466B1

    公开(公告)日：2003-04-15

    申请号：US09657143

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.

    摘要翻译： 在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能 。 在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。 对于程序中的初始擦除周期，施加初始负栅极电压。 在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。 在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。 在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

    Single bit array edges
    4.
    发明授权
    Single bit array edges 有权
    单位阵列边缘

    公开(公告)号：US06493261B1

    公开(公告)日：2002-12-10

    申请号：US09795865

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

    摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

    摘要翻译： 在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。 虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。 通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

    High voltage transistor with low body effect and low leakage
    6.
    发明授权
    High voltage transistor with low body effect and low leakage 有权
    具有低体积效应和低泄漏的高压晶体管

    公开(公告)号：US06369433B1

    公开(公告)日：2002-04-09

    申请号：US09182525

    申请日：1998-10-30

    申请人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang

    发明人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang

    IPC分类号： H01L2994

    CPC分类号： H01L29/66575 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1041 ,  H01L29/66825

    摘要： A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.

    摘要翻译： 形成具有低泄漏和低体效应的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括在通道区域上提供场注入阻挡掩模，从而产生具有低体效应的晶体管，场注入阻挡掩模具有适当的开口，使得场注入发生在通道的边缘，从而减少泄漏。

    Positive gate erasure for non-volatile memory cells
    8.
    发明授权
    Positive gate erasure for non-volatile memory cells 有权
    非易失性存储单元的正门擦除

    公开(公告)号：US06331952B1

    公开(公告)日：2001-12-18

    申请号：US09697810

    申请日：2000-10-26

    申请人： Janet S. Y. Wang ,  Narbeh Derhacobian ,  Ravi S. Sunkavalli

    发明人： Janet S. Y. Wang ,  Narbeh Derhacobian ,  Ravi S. Sunkavalli

    IPC分类号： G11C1604

    CPC分类号： G11C16/0475 ,  G11C16/14

    摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes simultaneously applying a first positive voltage across the gate and a second positive voltage to the first region, wherein the second positive voltage is greater than the first positive voltage.

    摘要翻译： 一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。 该方法包括同时对栅极施加第一正电压，向第一区施加第二正电压，其中第二正电压大于第一正电压。

    Method of maintaining constant erasing speeds for non-volatile memory cells
    9.
    发明授权
    Method of maintaining constant erasing speeds for non-volatile memory cells 有权
    保持非易失性存储单元的不断擦除速度的方法

    公开(公告)号：US06215702B1

    公开(公告)日：2001-04-10

    申请号：US09504696

    申请日：2000-02-16

    申请人： Narbeh Derhacobian ,  Shane C. Hollmer ,  Ravi S. Sunkavalli

    发明人： Narbeh Derhacobian ,  Shane C. Hollmer ,  Ravi S. Sunkavalli

    IPC分类号： G11C1134

    CPC分类号： H01L29/7923 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/14

    摘要： A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first cycle of voltages across the gate and the first region so that the first amount of charge is removed from the charge trapping region. A second amount of charge is written into the charge trapping region and subsequently a second cycle of one or more voltages is applied across the gate and the first region so that the second amount of charge is removed from the charge trapping region, wherein the initial applied voltage of the second cycle of voltages is equal to the final applied voltage of the first cycle of voltages.

    摘要翻译： 一种擦除具有第一区域和第二区域以及沟道上方的栅极的存储单元的方法，以及包含初始电荷量的电荷捕获区域。 该方法包括跨越栅极和第一区域施加电压的第一周期，使得从电荷俘获区域去除第一电荷量。 第二量的电荷被写入电荷俘获区域中，随后在栅极和第一区域两端施加一个或多个电压的第二周期，使得从电荷俘获区域去除第二电荷量，其中初始施加 电压的第二周期的电压等于第一周期电压的最终施加电压。

    Memory cells, devices and method with dynamic storage elements and programmable impedance shadow elements
    10.
    发明授权
    Memory cells, devices and method with dynamic storage elements and programmable impedance shadow elements 有权
    具有动态存储元件和可编程阻抗阴影元件的存储单元，器件和方法

    公开(公告)号：US08995173B1

    公开(公告)日：2015-03-31

    申请号：US13603373

    申请日：2012-09-04

    申请人： Narbeh Derhacobian

    发明人： Narbeh Derhacobian

    IPC分类号： G11C11/24 ,  G11C11/401

    CPC分类号： G11C11/401 ,  G11C13/0007 ,  G11C13/0011 ,  G11C14/0045

    摘要： A memory device can include a plurality of memory cells, each including a dynamic section configured to store data dynamically, and a programmable impedance section comprising at least one programmable element programmable between at least two different data states, the programmable impedance section configured to establish a data value stored by the dynamic section in response to a recall signal.

    摘要翻译： 存储器设备可以包括多个存储器单元，每个存储器单元包括动态部分，被配置为动态地存储数据，以及可编程阻抗部分，其包括在至少两个不同数据状态之间可编程的至少一个可编程元件，所述可编程阻抗部分被配置为建立 响应于召回信号由动态部分存储的数据值。