发明授权
- 专利标题： Nonvolatile semiconductor memory
- 专利标题（中）： 非易失性半导体存储器
-
申请号： US09812572申请日： 2001-03-21
-
公开(公告)号： US06442080B2公开(公告)日： 2002-08-27
- 发明人: Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
- 申请人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
- 优先权： JP11-074039 19990318; JP11-074045 19990318
- 主分类号： G11C1140
- IPC分类号： G11C1140
摘要：
A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
公开/授权文献
- US20020003723A1 Nonvolatile semiconductor memory 公开/授权日：2002-01-10
信息查询
