公开(公告)号：US08576317B2

公开(公告)日：2013-11-05

申请号：US13064338

申请日：2011-03-21

Applicant: Masaki Sakakibara ,  Tadayuki Taura ,  Yusuke Oike ,  Takafumi Takatsuka ,  Akihiko Kato

Inventor： Masaki Sakakibara ,  Tadayuki Taura ,  Yusuke Oike ,  Takafumi Takatsuka ,  Akihiko Kato

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/335 ,  H04N5/355 ,  H04N5/3575 ,  H04N5/365 ,  H04N5/3698 ,  H04N5/3745 ,  H04N5/378

Abstract: Disclosed herein is a solid-state image pickup apparatus, including a pixel array section in which a unit pixel including a photoelectric conversion section and a charge detection section for detecting charge generated by photoelectric conversion by the photoelectric conversion section is disposed; a driving section adapted to carry out driving of reading out a signal of the unit pixel divisionally by twice as a first signal and a second signal; and a signal processing section adapted to set the first signal read out first from the unit pixel as a reference voltage for a processable input voltage range of the signal processing section, adjust the reference voltage so that the first and second signals may be included in the input voltage range and carry out signal processing for the first and second signals using the adjusted reference voltage.

Abstract translation: 本发明公开了一种固态摄像装置，包括像素阵列部分，其中设置有包括光电转换部分的单位像素和用于检测光电转换部分由光电转换产生的电荷的电荷检测部分; 驱动部，其适于执行将所述单位像素的信号分别读出作为第一信号和第二信号的两倍的驱动; 以及信号处理部，其适于将从单位像素首先读出的第一信号设置为信号处理部的可处理输入电压范围的参考电压，调整参考电压，使得第一和第二信号可以包括在 输入电压范围，并使用调整的参考电压对第一和第二信号进行信号处理。

公开(公告)号：US08072521B2

公开(公告)日：2011-12-06

申请号：US11668643

申请日：2007-01-30

Applicant: Akihiko Kato ,  Tadayuki Taura ,  Yoshinori Muramatsu

Inventor： Akihiko Kato ,  Tadayuki Taura ,  Yoshinori Muramatsu

IPC: H04N3/14

CPC classification number: H04N5/378 ,  H04N5/3454 ,  H04N5/361 ,  H04N5/3742 ,  H04N5/376

Abstract: A solid state imaging device with pixels in a two-dimensional array, a controller which performs window cutting on signals read out of the pixel array in multiple column units on a column-address basis, and a selector which, when the cutting window overlaps with a multiple column unit, holds signals in a present multiple column unit and in a previous column unit, and then outputs selected consecutive signals.

Abstract translation: 具有二维阵列中的像素的固态成像装置，以列地址为基础以多列单位从像素阵列读出的信号执行窗口切割的控制器，以及当切割窗口与 多列单元，保持当前多列单元和先前列单元中的信号，然后输出所选择的连续信号。

公开(公告)号：US08054354B2

公开(公告)日：2011-11-08

申请号：US12080851

申请日：2008-04-07

Applicant: Tadayuki Taura

Inventor： Tadayuki Taura

IPC: H04N3/14 ,  H04N5/335 ,  H04N17/00 ,  H04N17/02

CPC classification number: H04N5/772 ,  H04N5/335 ,  H04N5/374 ,  H04N5/378 ,  H04N5/907

Abstract: A data transfer circuit includes at least one data transfer line that transfers digital data, at least one data detecting circuit connected to the transfer line, holding circuits that hold digital values corresponding to input levels and that transfer the digital values to the transfer line, a scanning circuit that selects a holding circuit from among the holding circuits, at least one test-pattern generating circuit that generates a predetermined digital value, the test-pattern generating circuit being connected to the transfer line, at least one test-column scanning circuit that selects the test-pattern generating circuit, and a start-pulse selecting circuit that controls starting of the scanning circuit and starting of the test-column scanning circuit. The start-pulse selecting circuit has a function of transferring the predetermined digital value to the data transfer line by activating the test-pattern generating circuit via the test-column scanning circuit.

Abstract translation: 数据传输电路包括传送数字数据的至少一个数据传输线，连接到传输线的至少一个数据检测电路，保持对应于输入电平的数字值并将数字值传送到传送线的保持电路， 从保持电路中选择保持电路的扫描电路，产生预定数字值的至少一个测试图案生成电路，连接到传送线的测试图案生成电路，至少一个测试列扫描电路， 选择测试图形生成电路，以及控制扫描电路的启动和测试列扫描电路的启动的启动脉冲选择电路。 启动脉冲选择电路具有通过测试列扫描电路激活测试图形生成电路将预定数字值传送到数据传输线的功能。

公开(公告)号：US20100225776A1

公开(公告)日：2010-09-09

申请号：US12711356

申请日：2010-02-24

Applicant: Tadayuki Taura

Inventor： Tadayuki Taura

IPC: H04N5/335 ,  H01L31/18 ,  H04N5/228

CPC classification number: H01L27/14623 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14687 ,  H01L27/14689

Abstract: A solid-state imaging device includes a photodetector which is formed on a substrate and is configured to generate signal charge by photoelectric conversion, a floating diffusion configured to receive the signal charge generated by the photodetector, a plurality of MOS transistors including a transfer transistor that transfers the signal charge to the floating diffusion and an amplification transistor that outputs an pixel signal corresponding to a potential of the floating diffusion, a multi-wiring layer which is formed in a layer higher than the substrate and is composed of a plurality of wiring layers electrically connected to the MOS transistors via contact portions, and a light-shielding film that is constituted by a bottom wiring layer disposed in a layer higher than the substrate and lower than the multi-wiring layer.

Abstract translation: 一种固态成像装置，包括形成在基板上并被配置为通过光电转换产生信号电荷的光电检测器，被配置为接收由光电检测器产生的信号电荷的浮动扩散，多个MOS晶体管，包括转移晶体管， 将信号电荷传送到浮动扩散部，以及输出与浮动扩散电位相对应的像素信号的放大晶体管，形成在比基板高的层中的多层布线层 通过接触部电连接到MOS晶体管，以及遮光膜，其由布置在比该衬底高于多层布线的层中的底部布线层构成。

公开(公告)号：US20090109315A1

公开(公告)日：2009-04-30

申请号：US12246026

申请日：2008-10-06

Applicant: Tadayuki Taura

Inventor： Tadayuki Taura

IPC: H04N5/335 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03K21/08 ,  H03M1/1023 ,  H03M1/123 ,  H03M1/56 ,  H04N5/37455 ,  H04N5/378

Abstract: A data processor includes: a reference signal generator generating a reference signal that gradually varies to enhance an amplitude of the processing signal; a comparator comparing the processing signal with the reference signal generated by the reference signal generator; a count period controller determining to perform a real number count operation or a complement number count operation; a counter performing the count operation during the count period determined by the count period controller and acquiring a predetermined level of digital data by storing the count value at the time of completion of the count operation; and a corrector acquiring the digital data as a value of a real number by correcting the complement number count operation. The count period controller independently controls the real number count operation and the complement number count operation of the counter on the basis of a predetermined criterion.

Abstract translation: 数据处理器包括：参考信号发生器，产生逐渐变化的参考信号，以增强处理信号的幅度; 将所述处理信号与由所述参考信号发生器产生的参考信号进行比较的比较器; 计数周期控制器确定执行实数计数操作或补数计数操作; 计数器，在由计数周期控制器确定的计数期间内执行计数操作，并通过存储计数操作完成时的计数值来获取预定数量数据; 以及校正器，通过校正补数计数操作来获取数字数据作为实数值。 计数周期控制器基于预定标准独立地控制计数器的实数计数操作和补数计数操作。

公开(公告)号：US20080135729A1

公开(公告)日：2008-06-12

申请号：US11860196

申请日：2007-09-24

Applicant: Tadayuki Taura

Inventor： Tadayuki Taura

IPC: H01L27/00 ,  H04N5/235

CPC classification number: H04N5/335 ,  H03M1/1023 ,  H03M1/1295 ,  H03M1/56 ,  H04N5/3765 ,  H04N5/378

Abstract: A method of driving a solid-image-pickup device is provided. The driving method includes the steps of converting light incident on a plurality of pixels arranged in matrix form into an electric signal, selecting and controlling the pixels for each of rows and/or columns, and scanning the pixels in sequence, converting at least one analog signal obtained from at least one of the selected and controlled pixels into a first digital signal, the at least one pixel corresponding to a first group of rows and/or columns, and performing first counting for data on a result of the conversion, and converting at least one analog signal obtained from at least one of the selected and controlled pixels into a second digital signal, the at least one pixel corresponding to a second group of rows and/or columns, and performing second counting for data on a result of the conversion. A period where the first counting is performed is separate from a period where the second counting is performed.

Abstract translation: 提供了一种驱动固体摄像装置的方法。 驱动方法包括以下步骤：将以矩阵形式布置的多个像素入射的光转换为电信号，选择和控制每行和/或列的像素，并依次扫描像素，将至少一个模拟 从所选择的和受控像素中的至少一个获得的信号变为第一数字信号，所述至少一个像素对应于第一组行和/或列，并且对转换结果的数据执行第一计数，以及转换 从所选择的和受控的像素中的至少一个获得的至少一个模拟信号成为第二数字信号，所述至少一个像素对应于第二组行和/或列，并且对于关于 转换。 执行第一计数的时间段与执行第二次计数的时间段不同。

公开(公告)号：US07120053B2

公开(公告)日：2006-10-10

申请号：US11033398

申请日：2005-01-12

Applicant: Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

Inventor： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

IPC: G11C16/22

CPC classification number: G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.

Abstract translation: 半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。 熔丝单元字线形成在与主单元字线的方向相同的方向上。

公开(公告)号：US06707733B2

公开(公告)日：2004-03-16

申请号：US10318020

申请日：2002-12-13

Applicant: Tadayuki Taura ,  Shigeru Atsumi ,  Shuji Maeda

Inventor： Tadayuki Taura ,  Shigeru Atsumi ,  Shuji Maeda

IPC: G11C700

CPC classification number: G11C29/81

Abstract: A semiconductor memory device comprises memory cell blocks, a first redundancy cell array for each of the memory blocks, a redundancy cell block, a second redundancy cell array for the redundancy block, a first defect rescuing circuit configured to output a replacement signal for replacing a defective cell array in the redundancy block with the first redundancy array, and a second defect rescuing circuit configured to output a replacement signal for replacing a defective memory block with the redundancy block, wherein the first defect rescuing circuit has a gate circuit which outputs the output replacement signal of the first address sensing circuit as valid at an address at which the second defect rescuing circuit is not implemented, and which outputs a signal indicating which block is a defective block outputted by the second defect rescuing circuit as valid at an address at which the second defect rescuing circuit is implemented.

Abstract translation: 半导体存储器件包括存储器单元块，用于每个存储器块的第一冗余单元阵列，冗余单元块，用于冗余块的第二冗余单元阵列，第一缺陷抢救电路，被配置为输出用于替换 具有第一冗余阵列的冗余块中的有缺陷的单元阵列，以及第二缺陷抢救电路，配置为输出用冗余块替换缺陷存储块的替换信号，其中第一缺陷抢救电路具有输出输出的门电路 第一地址感测电路的替换信号在没有实现第二缺陷抢救电路的地址处有效，并且在第二个缺陷抢救电路的地址输出指示哪个块是由第二个缺陷抢救电路输出的有缺陷的块的信号是有效的， 执行第二个缺陷抢救电路。

公开(公告)号：US06535427B1

公开(公告)日：2003-03-18

申请号：US09707983

申请日：2000-11-08

Applicant: Yoshinori Takano ,  Toru Tanzawa ,  Tadayuki Taura

Inventor： Yoshinori Takano ,  Toru Tanzawa ,  Tadayuki Taura

IPC: G11C1626

CPC classification number: G11C7/12 ,  G11C7/20 ,  G11C16/24 ,  G11C16/26

Abstract: A memory cell is connected to a cell-based bit line. The cell-based bit line is connected to a bit line via a Y decoder. The bit line is connected to a sense bit line via a separation circuit. This sense bit line is connected to a sense line via a bias circuit. An amplifier circuit amplifies a signal voltage on the sense line together with a reference voltage for sensing data. The sense line is connected with a sense line initialization circuit for setting the sense line to a specified voltage. The bit line is connected with a bit line initialization circuit for setting the bit line to a specified voltage. Both the sense line initialization circuit and the bit line initialization circuit are activated in a given period before the amplifier circuit operates to sense data. Thus, the sense line and the bit line are set to specified voltages.

Abstract translation: 存储单元连接到基于单元的位线。 基于单元的位线通过Y解码器连接到位线。 位线通过分离电路连接到感测位线。 该感测位线通过偏置电路连接到感测线。 放大器电路将感测线上的信号电压与用于感测数据的参考电压一起放大。 感测线与感测线初始化电路连接，用于将感测线设置为指定电压。 位线与位线初始化电路连接，用于将位线设置为指定电压。 感测线初始化电路和位线初始化电路在放大器电路操作以感测数据之前的给定时间段内被激活。 因此，感测线和位线被设定为规定的电压。

公开(公告)号：US06510089B2

公开(公告)日：2003-01-21

申请号：US10186683

申请日：2002-07-02

Applicant: Tadayuki Taura ,  Shigeru Atsumi

Inventor： Tadayuki Taura ,  Shigeru Atsumi

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C5/145

Abstract: A voltage-level shifter has a first and a second power supply terminal to which a first and a second potential are supplied, respectively, the second potential being lower than the first potential; a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal. The voltage-level shifter also has a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal; a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal; a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal; a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal; a third NMOS transistor having a source connected to the second power supply terminal, drain connected to the source of the first NMOS transistor, and a gate connected to the second output terminal; and a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the first output terminal.

Abstract translation: 电压电平移位器具有分别提供第一和第二电位的第一和第二电源端子，第二电位低于第一电位; 提供第一输入信号的第一输入端，所述第一输入信号具有根据所述第一和第二电位的高电平和低电平; 提供第二输入信号的第二输入端，第二输入信号是第一输入信号的反相信号。 电压电平移位器还具有第一PMOS晶体管，源极连接到第一电源端子，栅极连接到第一输入端子，漏极连接到第一输出端子，用于输出第一输出信号; 第二PMOS晶体管，具有连接到第一电源端子的源极，连接到第二输入端子的栅极和连接到第二输出端子的漏极，用于输出作为第一输出信号的反相信号的第二输出信号; 第一NMOS晶体管，其漏极连接到第一输出端子，栅极连接到第一输入端子; 第二NMOS晶体管，具有连接到第二输出端子的漏极和连接到第二输入端子的栅极; 第三NMOS晶体管，其源极连接到第二电源端子，连接到第一NMOS晶体管的源极的漏极和连接到第二输出端子的栅极; 以及第四NMOS晶体管，其源极连接到第二电源端子，漏极连接到第二NMOS晶体管的源极，栅极连接到第一输出端子。