发明授权
US06442633B1 Reduced transistors data switch port wherein each of a plurality of transmission gates is coupled to both first and second control signals for selectively enabling
有权
减少的晶体管数据交换端口，其中多个传输门中的每一个耦合到第一和第二控制信号以用于选择性地启用
- 专利标题： Reduced transistors data switch port wherein each of a plurality of transmission gates is coupled to both first and second control signals for selectively enabling
- 专利标题（中）： 减少的晶体管数据交换端口，其中多个传输门中的每一个耦合到第一和第二控制信号以用于选择性地启用
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申请号： US09275279申请日： 1999-03-23
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公开(公告)号： US06442633B1公开(公告)日： 2002-08-27
- 发明人: Augustine W. Chang
- 申请人： Augustine W. Chang
- 主分类号： G06F1314
- IPC分类号： G06F1314
摘要：
A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.
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