公开(公告)号：US07082056B2

公开(公告)日：2006-07-25

申请号：US10800228

申请日：2004-03-12

申请人： Ben Wei Chen ,  Augustine W. Chang

发明人： Ben Wei Chen ,  Augustine W. Chang

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C7/1006 ,  G11C2211/5631 ,  G11C2211/5634

摘要： A FLASH memory has an array of FLASH cells that each store N multiple bits of information as charge stored on a floating gate. Reference voltages or currents are generated for each boundary between the 2N states or levels and for an upper limit and a lower limit reference for each state. A selected bit line driven by a selected FLASH cell generates a sense node that is compared to a full range of 3*2N−1 comparators in parallel. The compare results are decoded to determine which state is read from the selected FLASH cell. An in-range signal is activated when the sense node is between the upper and lower limit references. The target programming count or programming pulses is adjusted during calibration to sense in the middle of the upper and lower limit references. Margin between references is adjusted by calibration codes that select currents for summing.

摘要翻译： FLASH存储器具有闪存单元的阵列，每个存储N个多位信息作为存储在浮动栅极上的电荷。 对于两个状态或电平之间的每个边界以及每个状态的上限和下限参考产生参考电压或电流。 由所选择的FLASH单元驱动的所选位线产生与3×2×N + 1比较器的全范围并行比较的感测节点。 解码比较结果以确定从所选择的FLASH单元读取哪个状态。 当感测节点在上限和下限参考之间时，范围内信号被激活。 在校准期间调整目标编程计数或编程脉冲，以在上限和下限参考值的中间进行感测。 参考值之间的余量是通过选择用于求和的电流的校准码进行调整的。

公开(公告)号：US4228450A

公开(公告)日：1980-10-14

申请号：US844768

申请日：1977-10-25

申请人： Narasipur G. Anantha ,  Augustine W. Chang

发明人： Narasipur G. Anantha ,  Augustine W. Chang

IPC分类号： H01L27/04 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/82 ,  H01L21/822 ,  H01L27/08 ,  H01L27/118 ,  H01L29/73 ,  H01L29/8605 ,  H01L29/861 ,  H01L27/02

CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L27/0802 ,  H01L29/8605

摘要： A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.

摘要翻译： 给出了一种用于高密度集成电路的高电阻结构及其制造方法。 该结构包括通过围绕该区域的介电阻挡层与其它硅区域分离的硅区域。 第一电导率的电阻器，例如N型，基本上包含硅区域的表面。 对电阻器进行电接触。 高度掺杂第二电导率的区域，例如P型，位于电阻区域的一部分的下方。 该第二导电区域连接到表面。 为了偏压目的，将电触头制成该变化区域。 可以将同一隔离硅区域内的第二区域用作电阻器。 该区域位于第二导电性的掩埋区域的下方。 或者，所描述的电阻器区域可以作为晶体管连接。 这允许形成标准的主机，其可以在制造的后期被个性化到标准区域的全部或一部分中的电阻器或晶体管。

公开(公告)号：US07375548B2

公开(公告)日：2008-05-20

申请号：US11525749

申请日：2006-09-22

申请人： Augustine W. Chang

发明人： Augustine W. Chang

IPC分类号： G06F7/38 ,  G03K19/173

CPC分类号： G06F17/5054 ,  G11C16/0416 ,  G11C16/0483 ,  H03K19/0002

摘要： A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention. Accordingly, the present invention includes control schemes to field program basic circuit element or any critical nets, and to alter the functionality of certain predetermined circuit units, and update array interconnections, accessing stored protocols, algorithms in all chips in the embodiment subsystem of a SFPGA chip sets.

摘要翻译： 提出了一种新的Schottky FPGA（SFPGA）IC解决方案。 该芯片由具有片上设备和软件的嵌入式模拟，存储器和逻辑单元组织，以分割，更改硬件的所选部分。 处理手段基于组合的肖特基CMOS（SCMOS，美国专利号6,590,800）和闪存技术。 电路方式是基于SCMOS-DTL门阵列。 软件手段是基于具有LUT级别的C ++程序。 SFPGA器件支持具有嵌入式模拟，逻辑和存储器阵列单元的GHz低功耗ASIC混合信号产品应用。 公开了几种复用方案，其适应任务来改变所选晶体管或IO网络的Vt和传输线传输，并因此改变其模拟和数字设备属性。 根据本发明还公开了倍压器和电源升压器以及数字模拟数字转换器（DADT）装置。 因此，本发明包括对现场程序基本电路元件或任何关键网络的控制方案，并且改变某些预定电路单元的功能，以及更新阵列互连，访问存储的协议，在SFPGA的实施例子系统中的所有芯片中的算法 芯片组。

公开(公告)号：US06442633B1

公开(公告)日：2002-08-27

申请号：US09275279

申请日：1999-03-23

申请人： Augustine W. Chang

发明人： Augustine W. Chang

IPC分类号： G06F1314

CPC分类号： H03K17/002 ,  H03K17/693

摘要： A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.

摘要翻译： 为高级IC设计的矢量交换端口应用提出了高密度，高速和低功率电路方案。 实施例具有优异的面积延迟功率特性。 该技术有利于广泛的产品应用，从高速高带宽路由器到低功耗便携式计算硬件。 片上矢量端口可支持5.0 TBPS峰值流量。

公开(公告)号：US4135954A

公开(公告)日：1979-01-23

申请号：US814801

申请日：1977-07-12

申请人： Augustine W. Chang ,  Arun K. Gaind

发明人： Augustine W. Chang ,  Arun K. Gaind

IPC分类号： H01L21/76 ,  H01L21/306 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/22 ,  H01L21/316

CPC分类号： H01L29/66272 ,  H01L21/8238 ,  Y10S438/942

摘要： A method for fabricating self-aligned regions of semiconductor devices such as bipolar or field effect transistors using three masking layers which are selectively etchable with respect to each other on the surface of the semiconductor body. A dimensional mask is deposited over the three layers so that the set of all of the self-aligned impurity regions to be formed through the surface of the body are defined by etching the upper masking layer, with the intermediate layer acting as an etch-stop. Using conventional wet or dry resist processes, each subset of similar impurity regions may then be formed selectively through the intermediate and lower layers without the need for precisely aligning any subsequent mask.

摘要翻译： IC是mfrd 通过（a）形成叠加的第一，第二和第三掩蔽层，可选择性地刻蚀w.r.t. （b）仅在第一层中蚀刻一组开口（c）通过使用第一层作为掩模的至少第二层蚀刻该组内的第一开口子集，同时 保护剩余的开口，（d）通过第一开口子集在基板中形成第一区域，以及（e）使用第二和第三开口子集类似地形成第二和第三区域。 区域是自对准的，没有底切形成，允许减小设备尺寸并减小它们之间的距离。 -

公开(公告)号：US07135890B2

公开(公告)日：2006-11-14

申请号：US10827786

申请日：2004-04-19

申请人： Augustine W. Chang

发明人： Augustine W. Chang

IPC分类号： H03K19/00

CPC分类号： G06F17/5054 ,  G11C16/0416 ,  G11C16/0483 ,  H03K19/0002

摘要： A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention.Accordingly, the present invention includes control schemes to field program basic circuit element or any critical nets, and to alter the functionality of certain predetermined circuit units, and update array interconnections, accessing stored protocols, algorithms in all chips in the embodiment subsystem of a SFPGA chip sets.

摘要翻译： 提出了一种新的Schottky FPGA（SFPGA）IC解决方案。 该芯片由具有片上设备和软件的嵌入式模拟，存储器和逻辑单元组织，以分割，更改硬件的所选部分。 处理手段基于组合的肖特基CMOS（SCMOS，美国专利号6,590,800）和闪存技术。 电路方式是基于SCMOS-DTL门阵列。 软件手段是基于具有LUT级别的C ++程序。 SFPGA器件支持具有嵌入式模拟，逻辑和存储器阵列单元的GHz低功耗ASIC混合信号产品应用。 公开了几种复用方案，其适应任务来改变所选晶体管或IO网络的Vt和传输线传输，并因此改变其模拟和数字设备属性。 根据本发明还公开了倍压器和电源升压器以及数字模拟数字转换器（DADT）装置。 因此，本发明包括对现场程序基本电路元件或任何关键网络的控制方案，并且改变某些预定电路单元的功能，以及更新阵列互连，访问存储的协议，在SFPGA的实施例子系统中的所有芯片中的算法 芯片组。

公开(公告)号：US4316319A

公开(公告)日：1982-02-23

申请号：US141717

申请日：1980-04-18

申请人： Narasipur G. Anantha ,  Augustine W. Chang

发明人： Narasipur G. Anantha ,  Augustine W. Chang

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L27/08 ,  H01L29/8605 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/8222 ,  H01L21/743 ,  H01L27/0802 ,  H01L29/8605

摘要： A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.

摘要翻译： 给出了一种用于高密度集成电路的高电阻结构及其制造方法。 该结构包括通过围绕该区域的介电阻挡层与其它硅区域分离的硅区域。 第一电导率的电阻器，例如N型，基本上包含硅区域的表面。 对电阻器进行电接触。 高度掺杂第二电导率的区域，例如P型，位于电阻区域的一部分的下方。 该第二导电区域连接到表面。 为了偏压目的，将电触头制成该变化区域。 可以将同一隔离硅区域内的第二区域用作电阻器。 该区域位于第二导电性的掩埋区域的下方。 或者，所描述的电阻器区域可以作为晶体管连接。 这允许形成标准的主机，其可以在制造的后期被个性化到标准区域的全部或一部分中的电阻器或晶体管。