发明授权
US06442701B1 Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words
有权
通过在取出多个指令字期间禁用对齐的NOP插槽的存储器块访问来节省功率
- 专利标题： Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words
- 专利标题（中）： 通过在取出多个指令字期间禁用对齐的NOP插槽的存储器块访问来节省功率
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申请号： US09415526申请日： 1999-10-08
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公开(公告)号： US06442701B1公开(公告)日： 2002-08-27
- 发明人: Linda L. Hurd
- 申请人： Linda L. Hurd
- 主分类号： G06F132
- IPC分类号： G06F132
摘要：
A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, such that NOPs instructions are aligned in the same slot from one instruction to the next for a series of instructions. This modification permits memory access to be disabled so that those instructions are not fetched.
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