A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.