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公开(公告)号：US06445046B1
公开(公告)日：2002-09-03
申请号：US09331034
申请日：1999-06-15
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
IPC分类号： H01L29772
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L27/11517
摘要： A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.
摘要翻译： 多个彼此绝缘的存储器单元线路，并且分别包括第一掺杂区域和第二掺杂区域，在该第二掺杂区域和第二掺杂区域之间包含具有电荷载流子阱的材料和多个栅电极的栅极电介质。 相邻栅电极的间隔小于栅电极的尺寸。 通过将电荷载体引入栅极电介质来存储信息。 优选地，通过间隔物技术来制造栅电极。
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公开(公告)号：US6153475A
公开(公告)日：2000-11-28
申请号：US331495
申请日：1999-06-21
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/336
CPC分类号： H01L27/112
摘要： For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.
摘要翻译： PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102（e）日期1999年6月21日PCT 1997年11月4日PCT PCT。 第WO98 / 27586号公报 日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置，由此存储单元沿带状沟槽的相对边缘布置 沿着沟槽（5）相邻的存储单元依次制造。 特别是通过间隔物技术来确定相邻存储单元的间隔。 通过这种方式，可以实现1F2的每个存储单元的空间要求，由此F是相应技术的最小结构尺寸。
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公开(公告)号：US6040995A
公开(公告)日：2000-03-21
申请号：US230614
申请日：1999-01-28
申请人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
发明人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
IPC分类号： H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/02
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792
摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.
摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。
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4.发明授权Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement 失效用于制造电可写和可擦除的只读存储单元布置的方法
公开(公告)号：US5882969A
公开(公告)日：1999-03-16
申请号：US967419
申请日：1997-11-11
IPC分类号： H01L21/822 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/8221 , H01L27/11551
摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.
摘要翻译： 在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。 因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。 控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。 实现2F2（F最小结构尺寸）每个存储单元的表面要求。
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5.发明授权
公开(公告)号：US6125050A
公开(公告)日：2000-09-26
申请号：US335365
申请日：1999-06-17
IPC分类号： H01L27/112 , G11C5/02 , H01L21/8246
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.
摘要翻译： 平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。 多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。 每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。
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6.发明授权Electrically programmable memory cell array, using charge carrier traps and insulation trenches 失效电可编程存储单元阵列，使用电荷载流子阱和绝缘沟槽公开(公告)号：US06191459B1
公开(公告)日：2001-02-20
申请号：US08780488
申请日：1997-01-08
IPC分类号： H01L2976
CPC分类号： H01L29/7926 , H01L27/115 , H01L27/11556 , H01L29/792
摘要： An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.
摘要翻译： 电可编程存储单元阵列由包括垂直MOS晶体管的存储单元形成。 MOS晶体管具有具有电荷载流子阱的材料的栅极电介质。 存储单元沿带状平行绝缘沟槽的相对边缘设置。 绝缘沟槽的宽度和间距优选相同。 存储单元阵列每个存储单元所需的空间为2F2，其中F为所采用技术中的最小结构尺寸。 通过选择性地将电子注入到栅极电介质中来对存储器单元进行编程。
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公开(公告)号：US5994746A
公开(公告)日：1999-11-30
申请号：US232083
申请日：1999-01-15
IPC分类号： G11C17/08 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115
CPC分类号： H01L27/11273 , H01L27/112
摘要： The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.
摘要翻译： 存储单元具有三维布置的晶体管。 垂直MOS晶体管布置在半导体薄片的侧壁上，并且多个晶体管彼此并排设置在每个侧壁上。 在侧壁上一个上下配置的晶体管串联连接。
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公开(公告)号：US06576948B2
公开(公告)日：2003-06-10
申请号：US09873231
申请日：2001-06-04
IPC分类号： H01L27108
CPC分类号： H01L27/108
摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.
摘要翻译： 集成电路包含平面第一晶体管和二极管。 二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。 作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。 作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。 二极管可以配置为隧道二极管。 二极管层可以通过热氧化生产。 制造二极管只需要一个掩模。 电容器可以设置在二极管的上方。 电容器的第一电容器电极连接到导电结构。
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公开(公告)号：US06475866B2
公开(公告)日：2002-11-05
申请号：US09774316
申请日：2001-01-31
IPC分类号： H01L21336
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译： 一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法，其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。 通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值，并且通过不同的沟道掺杂实现其它阈值电压值。 可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。
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公开(公告)号：US06399433B2
公开(公告)日：2002-06-04
申请号：US09773218
申请日：2001-01-31
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/55
摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
摘要翻译： 一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。 在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。 在该间隙中形成单元板电极，并在该层中形成沟槽。 沟槽达到第一插头表面的最远处，并且填充有绝缘层。 该层被删除。 形成具有高ε或铁电介质的存储电容器和存储节点电极。 电容器设置在身体内和上方的第二平面内。 绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。 第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。
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