发明授权
US06448602B1 Semiconductor memory device with improved arrangement of memory blocks and peripheral circuits
失效
具有改进的存储块和外围电路布置的半导体存储器件
- 专利标题： Semiconductor memory device with improved arrangement of memory blocks and peripheral circuits
- 专利标题（中）： 具有改进的存储块和外围电路布置的半导体存储器件
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申请号： US08627313申请日： 1996-04-03
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公开(公告)号： US06448602B1公开(公告)日： 2002-09-10
- 发明人: Narumi Sakashita , Kazutami Arimoto
- 申请人： Narumi Sakashita , Kazutami Arimoto
- 优先权： JP7-229175 19950906
- 主分类号： H01L3300
- IPC分类号： H01L3300
摘要：
A DRAM includes a semiconductor substrate and unit blocks. Each unit block includes a peripheral circuit and eight memory blocks arranged to surround the peripheral circuit. Each memory block includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a row decoder, and a column decoder.
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