公开(公告)号：US06448602B1

公开(公告)日：2002-09-10

申请号：US08627313

申请日：1996-04-03

申请人： Narumi Sakashita ,  Kazutami Arimoto

发明人： Narumi Sakashita ,  Kazutami Arimoto

IPC分类号： H01L3300

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/4097

摘要： A DRAM includes a semiconductor substrate and unit blocks. Each unit block includes a peripheral circuit and eight memory blocks arranged to surround the peripheral circuit. Each memory block includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a row decoder, and a column decoder.

摘要翻译： DRAM包括半导体衬底和单元块。 每个单元块包括外围电路和布置成围绕外围电路的八个存储器块。 每个存储块包括多个字线，多个位线，多个存储器单元，行解码器和列解码器。

公开(公告)号：US4903005A

公开(公告)日：1990-02-20

申请号：US250461

申请日：1988-09-28

申请人： Narumi Sakashita ,  Yukihiko Shimazu

发明人： Narumi Sakashita ,  Yukihiko Shimazu

IPC分类号： G06F7/02

CPC分类号： G06F7/026

摘要： A multiple digit comparator checks the first and the second input data for a match. If the two input data match, the carry input data from the previous digit is outputted as the carry output data for the next digit; if the two input data do not match, then a no match signal is outputted as the carry output data for the next digit. Next, if the carry input data and the carry output data do not match then a change point signal is outputted. When this change point signal is outputted, the first and the second input data are outputted. This facilitates the design of a more regular comparator circuit layout and of a faster comparator circuit.

摘要翻译： 多位数比较器检查第一和第二输入数据以进行匹配。 如果两个输入数据相匹配，则前一个数字的进位输入数据作为下一个数字的进位输出数据输出; 如果两个输入数据不匹配，则输出不匹配信号作为下个数字的进位输出数据。 接下来，如果进位输入数据和进位输出数据不匹配，则输出变化点信号。 当输出该变化点信号时，输出第一和第二输入数据。 这有助于设计更加规则的比较器电路布局和更快的比较器电路。

公开(公告)号：US5051997A

公开(公告)日：1991-09-24

申请号：US622316

申请日：1990-12-03

申请人： Narumi Sakashita ,  Yukihiko Shimazu

发明人： Narumi Sakashita ,  Yukihiko Shimazu

IPC分类号： G01R31/28 ,  G06F11/27 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F11/27

摘要： Apparatus is disclosed for a self-test function internal to a semiconductor integrated circuit. The invention includes an internal random number generator for generating test data for use by a self-test program. As a result of the invention, external equipment is not necessary for executing the self-test, internal memory for storing for self-test data can be decreased, and self-test can be performed readily by the user. Furthermore, since self-test result data is compressed so as to be compared with the data of prediction values, the data of the test result can be reduced for easy processing.

摘要翻译： 公开了用于半导体集成电路内部的自检功能的装置。 本发明包括一个内部随机数发生器，用于产生用于自检程序的测试数据。 作为本发明的结果，外部设备不需要执行自检，可以减少用于自检数据的存储的内部存储器，并且用户可以容易地进行自检。 此外，由于自检结果数据被压缩以便与预测值的数据进行比较，因此可以减少测试结果的数据以便于处理。

公开(公告)号：US5708761A

公开(公告)日：1998-01-13

申请号：US403421

申请日：1995-03-14

申请人： Yasuhiko Nitta ,  Narumi Sakashita ,  Kenichi Shimomura ,  Shinji Komori

发明人： Yasuhiko Nitta ,  Narumi Sakashita ,  Kenichi Shimomura ,  Shinji Komori

IPC分类号： G06F9/06 ,  G05B13/02 ,  G06F9/44 ,  G06N5/04 ,  G06N7/02 ,  G06F15/00

CPC分类号： G06N5/048 ,  G06N7/026 ,  Y10S706/90

摘要： A fuzzy development-support device includes a data input unit, a fuzzy-inference execution unit and a result verification unit. As an example, the data input unit includes a display unit connected to a membership function generator and a grid pitch designation unit for designating a grid pitch on a grid sheet displayed on the display unit for creation of membership functions. The grid pitch designation unit allows variation of grid pitch on the grid sheet. Thus, an operator uses the grid pitch designation unit to achieve an effective input of membership functions by generating the grid sheet with a pitch adequate for a desired shape of membership function.

摘要翻译： 模糊开发支持装置包括数据输入单元，模糊推理执行单元和结果验证单元。 作为示例，数据输入单元包括连接到隶属函数发生器的显示单元和用于指定在显示单元上显示的网格板上的网格间距的网格间距指定单元，用于创建隶属函数。 网格间距指定单元允许网格上的网格间距变化。 因此，操作者使用网格间距指定单元通过产生具有适合于所需形状的隶属函数的间距的网格表来实现成员函数的有效输入。

公开(公告)号：US06636110B1

公开(公告)日：2003-10-21

申请号：US09300850

申请日：1999-04-28

申请人： Tsukasa Ooishi ,  Narumi Sakashita

发明人： Tsukasa Ooishi ,  Narumi Sakashita

IPC分类号： H01L2500

CPC分类号： G11C7/1093 ,  G06F1/10 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： To input buffers included in a peripheral pad group inputting an external signal and a DQ pad group for data input/output, clock signals from a synchronizing circuit are transmitted through a clock distributing circuit having a plurality of clock transmission nodes arranged in a shape of a tree. The synchronizing circuit accomplishes phase synchronization between a signal from a node nearest to the clock distributing circuit with an external clock signal. Thus, a skew in clock signals applied to the input and output buffers can be eliminated.

摘要翻译： 为了输入包括在输入外部信号的外围装置组组中的缓冲器和用于数据输入/输出的DQ焊盘组，来自同步电路的时钟信号通过时钟分配电路发送，该时钟分配电路具有多个时钟传输节点， 树。 同步电路利用外部时钟信号实现来自最靠近时钟分配电路的节点的信号之间的相位同步。 因此，可以消除施加到输入和输出缓冲器的时钟信号的偏斜。

公开(公告)号：US4813019A

公开(公告)日：1989-03-14

申请号：US111048

申请日：1987-10-21

申请人： Yukihiko Shimazu ,  Narumi Sakashita

发明人： Yukihiko Shimazu ,  Narumi Sakashita

IPC分类号： G06F9/30 ,  G06F9/22 ,  G06F9/318 ,  G11C13/00

CPC分类号： G06F9/223

摘要： A semiconductor integrated circuit includes an auxiliary instruction register group having a plurality of auxiliary instruction registers capable of setting in advance the content by a program, and one of the auxiliary instruction register selected by the output of the decoder or controls a portion of the semiconductor integrated circuit that is not controlled by the instruction of the instruction register or controls a portion while cooperating with the instruction register. Thus, the integrated circuit can effectively perform a control of large degree of freedoms in a short instruction register.

摘要翻译： 半导体集成电路包括具有多个辅助指令寄存器组的辅助指令寄存器组，该多个辅助指令寄存器能够预先通过程序设置内容，以及由解码器的输出选择的一个辅助指令寄存器，或者控制半导体集成的一部分 电路不受指令寄存器的指令控制，也可以与指令寄存器配合控制。 因此，集成电路可以有效地执行短指令寄存器中的大自由度的控制。

公开(公告)号：US20120085888A1

公开(公告)日：2012-04-12

申请号：US13239628

申请日：2011-09-22

申请人： Takefumi ENDO ,  Shinji KOMORI ,  Narumi SAKASHITA

发明人： Takefumi ENDO ,  Shinji KOMORI ,  Narumi SAKASHITA

IPC分类号： H01L27/146 ,  H01L31/119

CPC分类号： H01L27/1464 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14641

摘要： A back-side illuminated solid-state imaging device includes a photodiode and MOS transistors at a semiconductor substrate. The MOS transistors are formed over the front surface of the semiconductor substrate. The photodiode responds to an incident light applied to the back surface opposite to the front surface of the semiconductor substrate. A charge storing portion, and a first and second transfer gates are formed over the main part of the photodiode and the front surface of the semiconductor substrate located above the vicinity of the main part so as to achieve the global shutter function. Since the irradiation light is incident on the photodiode from the back surface of the semiconductor substrate in back-side illuminated solid-state imaging device, the sensitivity of the photodiode is not reduced even when the first and second transfer gates, and the charge storing portion are formed to achieve the global shutter function.

摘要翻译： 背面照明固体摄像器件包括在半导体衬底处的光电二极管和MOS晶体管。 MOS晶体管形成在半导体衬底的前表面上。 光电二极管响应于施加到与半导体衬底的前表面相对的背表面的入射光。 在光电二极管的主要部分和位于主要部分附近的半导体衬底的前表面上形成电荷存储部分和第一和第二传输门，以实现全局快门功能。 由于照射光从背面照明固态成像装置的半导体衬底的背面入射到光电二极管上，所以即使当第一和第二传输门和电荷存储部分 形成以实现全局快门功能。