发明授权
US06449204B1 DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL
失效
动态半导体存储器件，能够将数据存储从正常模式的单位/单个电池方案重新分配到双电池模式中的一个/两个电池模式，以增加刷新间隔
- 专利标题： DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL
- 专利标题（中）： 动态半导体存储器件，能够将数据存储从正常模式的单位/单个电池方案重新分配到双电池模式中的一个/两个电池模式，以增加刷新间隔
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申请号： US09817177申请日： 2001-03-27
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公开(公告)号： US06449204B1公开(公告)日： 2002-09-10
- 发明人: Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
- 申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
- 优先权： JP2000-094388(P) 20000330; JP2000-202001(P) 20000704; JP2000-290145(P) 20000925; JP2001-026769(P) 20010202
- 主分类号： G11C720
- IPC分类号： G11C720
摘要：
In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
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