An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit communicates in parallel with the ATM layer, and the second circuit communicates in parallel with the PHY layer. The extender circuit additionally includes a serial link which serially transmits signals between the first and second circuits. The serial link includes a first serial link for transmitting a first serial signal from the first circuit to the second circuit, and a second serial link transmitting a second serial signal from the second circuit to the first circuit. The first circuit and the second circuit include similar architecture. The first circuit includes a parallel interface circuit for communicating in parallel with the ATM layer and a serial interface circuit coupled to the parallel interface circuit for serially communicating with the second circuit. The parallel interface circuit includes control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit includes serializing/deserializing circuitry which includes serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals. The serializing/deserializing circuitry further includes deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the deserialized signals to the parallel interface circuit.