An apparatus and method of controlling instruction execution in the apparatus with a precise temporal execution arrangement. The apparatus may be a processor or microprocessor capable of executing a function specific wait state that is dependant upon a type specified by an instruction field. The processor includes a reference clock counter that maintains the wait count, an instruction parser that strips the wait type and count from instructions and passes the stripped information to a comparator. The comparator compares the stripped information against the wait count. The wait types include: a relative timestamp type indicating execution at some time subsequent to the present cycle; a direct timestamp type indicating an absolute time for execution; and a timestamp range indicating a time period when execution is valid.