A method of manufacturing chip scale packages at wafer level, comprising the steps of: a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes; b) forming a dam enclosing the perimeter of the wafer; c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and e) dicing the wafer according to the exposed scribe lines as positioning reference marks.