公开(公告)号：US06413801B1

公开(公告)日：2002-07-02

申请号：US09562903

申请日：2000-05-02

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2144

CPC classification number: H01L23/3121 ,  B29C45/02 ,  B29C45/14655 ,  B29C45/2669 ,  B29C45/34 ,  H01L21/565 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A method of molding a semiconductor device comprising the steps of: (a) providing a molding die comprising a molding portion having a cavity for accepting the semiconductor device, a dummy cavity connected to the cavity and an air vent connected to the dummy cavity; (b) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the cavity; (c) transferring a molding material into the cavity and the dummy cavity; (d) hardening the molding material; (e) unclamping and opening the molding die to take out the molded product. The molding method of the present invention is characterized in that even though the cavity with the semiconductor device positioned therein is filled, the transfer ram keeps moving such that the molding material is forced to continue flowing into the dummy cavity. This invention further provides a molding die for use in molding a semiconductor device. The molding die mainly comprises a pot for storing molding material, a molding portion and a runner. The molding portion has a cavity for accepting the semiconductor device, a dummy cavity connected to the cavity and an air vent connected to the dummy cavity. The runner has one end connected to the pot and the other end connected to the cavity through a gate. The channel for connecting the cavity to the dummy cavity has a size substantially the same as the size of the gate such that during molding, the molding material will fill the cavity through the runner and the gate, and then fill the dummy cavity through the channel.

Abstract translation: 一种模制半导体器件的方法，包括以下步骤：（a）提供一种模制模具，其包括具有用于接收半导体器件的空腔的模制部分，连接到模腔的虚拟空腔和连接到虚拟腔体的通风口; （b）以半导体芯片位于空腔中的方式封闭和夹紧模具; （c）将成型材料转移到空腔和虚拟空腔中; （d）硬化成型材料; （e）松开并打开模具以取出模制产品。 本发明的成型方法的特征在于，即使填充有位于其中的半导体器件的空腔，转印柱也保持移动，使得模制材料被迫继续流入虚拟空腔。 本发明还提供一种用于模制半导体器件的成型模具。 成型模具主要包括用于储存模制材料的模具，模制部分和浇道。 模制部分具有用于接收半导体器件的空腔，连接到空腔的虚拟腔和连接到虚拟腔的通气孔。 流道的一端连接到罐，另一端通过浇口连接到空腔。 用于将空腔连接到虚拟空腔的通道具有与门的尺寸基本相同的尺寸，使得在模制期间，模制材料将通过浇道和浇口填充空腔，然后通过通道填充虚拟空腔 。

公开(公告)号：US06534852B1

公开(公告)日：2003-03-18

申请号：US09547096

申请日：2000-04-11

Applicant: Chun Hung Lin ,  I Zeng Lee ,  Su Tao ,  Kun-Ching Chen

Inventor： Chun Hung Lin ,  I Zeng Lee ,  Su Tao ,  Kun-Ching Chen

IPC: H01L2352

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: Disclosed are metal reinforced layers disposed at the upper and lower surfaces of the thin substrate to reinforce the strength of the thin substrate. With reinforced strength, the thin substrate is not susceptible to deform due to temperature fluctuation during packaging process, and thus the warpage for the semiconductor package is significantly eliminated. According to another aspect of the present invention, the metal reinforced layer at the lower surface of the thin substrate is functioned as a ground plane for the ball grid array (BGA) semiconductor package for better grounding effect. The present invention provides an optimal design for the return current path and impedance matching control. Besides, in high frequency application, the metal reinforced layer also can reduce the noise and cross talk among the signal lines of the ball grid array (BGA) semiconductor package.

Abstract translation: 公开了设置在薄基板的上表面和下表面处的金属加强层，以增强薄基板的强度。 由于加强强度，薄的基板由于包装过程中的温度波动而不易变形，因此显着地消除了半导体封装的翘曲。 根据本发明的另一方面，薄基板的下表面处的金属增强层用作球栅阵列（BGA）半导体封装的接地平面，以获得更好的接地效果。 本发明为返回电流路径和阻抗匹配控制提供了最佳设计。 此外，在高频应用中，金属加强层还可以减少球栅阵列（BGA）半导体封装的信号线之间的噪声和串扰。

公开(公告)号：US06252305B1

公开(公告)日：2001-06-26

申请号：US09516025

申请日：2000-02-29

Applicant: Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao

Inventor： Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao

IPC: H01L2348

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/01087 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract translation: 多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。 半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线 芯片以允许其引线接合。 因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。 这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

公开(公告)号：US06573123B2

公开(公告)日：2003-06-03

申请号：US10029845

申请日：2001-12-31

Applicant: Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

Inventor： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

公开(公告)号：US06348399B1

公开(公告)日：2002-02-19

申请号：US09610857

申请日：2000-07-06

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: A method of making a chip scale package comprises the following steps: providing a semiconductor chip having a plurality of metal bumps formed on the active surface thereof; providing a metal plate having a plurality of flip-chip pads formed on a surface thereof; positioning the semiconductor chip on the surface of the metal plate with the metal bumps on the chip aligned with the flip-chip pads on the metal plate; connecting the metal bumps on the active surface of the semiconductor chip to the flip-chip pads on the surface of the metal plate; encapsulating the semiconductor chip against a portion of the surface of the metal plate; removing the metal plate while leaving the flip-chip pads intact; and forming a plurality of solder balls on the flip-chip pads. Using the technique of the present invention, it becomes possible that the manufacture of a molded chip scale package can be relatively simplified and economical, yet highly reliable.

Abstract translation: 制造芯片级封装的方法包括以下步骤：提供在其有效表面上形成有多个金属凸块的半导体芯片; 提供具有形成在其表面上的多个倒装芯片焊盘的金属板; 将半导体芯片定位在金属板的表面上，其中芯片上的金属凸块与金属板上的倒装芯片对准; 将半导体芯片的有源表面上的金属凸块连接到金属板表面上的倒装芯片焊盘; 将半导体芯片封装在金属板表面的一部分上; 去除金属板，同时使倒装芯片垫完好无损; 以及在所述倒装芯片焊盘上形成多个焊球。 使用本发明的技术，可以相对简单且经济地而且高度可靠地制造模制芯片级封装。

公开(公告)号：US06333562B1

公开(公告)日：2001-12-25

申请号：US09615836

申请日：2000-07-13

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2940

CPC classification number: H01L24/85 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/83136 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A multichip module mainly comprises two stacked chips disposed on and respectively wire bonded to a substrate or a lead frame. There are a plurality of electrically conductive bumps having base portions and pillar protruding portions interposed between the two chips. The conductive bumps are attached at their base portions to the bonding pads of the lower chip and connected at their pillar protruding portions to the backside surface of the upper chip so as to support the upper chip. In the multichip module of the present invention, the pillar protruding portions of bumps help to provide clearance between the two chips for keeping the upper chip from damaging the bonding wires of the lower chip.

Abstract translation: 多芯片模块主要包括两个堆叠的芯片，其布置在引线框架上并分别引线接合到基板或引线框架上。 存在多个导电凸块，其具有插入在两个芯片之间的基部和柱突出部。 导电凸块在其底部附着到下芯片的接合焊盘，并在其突出部分连接到上芯片的背面，以支撑上芯片。 在本发明的多芯片模块中，凸块的支柱突出部有助于在两个芯片之间提供间隙，以保持上部芯片不会损坏下部芯片的接合线。

公开(公告)号：US06700188B2

公开(公告)日：2004-03-02

申请号：US09854487

申请日：2001-05-15

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2348

CPC classification number: H01L21/568 ,  H01L21/4821 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K3/06 ,  H05K3/202 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.

Abstract translation: 包括用于接收半导体芯片的管芯焊盘和电耦合到半导体芯片的多个连接焊盘的低引脚数的芯片封装，其中管芯焊盘和连接焊盘具有凹形轮廓。 以半导体芯片，芯片焊盘和连接焊盘的方式形成封装主体，使得芯片焊盘的一部分和每个连接焊盘的一部分从封装主体的底部向外延伸。 本发明还提供了一种制造上述低引脚数芯片封装的新方法。

公开(公告)号：US06338813B1

公开(公告)日：2002-01-15

申请号：US09418569

申请日：1999-10-15

Applicant: Kao-Yu Hsu ,  Chun Hung Lin ,  Tao-Yu Chen

Inventor： Kao-Yu Hsu ,  Chun Hung Lin ,  Tao-Yu Chen

IPC: B29C4502

CPC classification number: B29C45/14655 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A molding method for a BGA semiconductor chip package comprising a substrate supporting an array of chips having two lines of bonding pads formed at two respective side thereof. The molding method comprises the steps of: (A) providing a molding apparatus comprising a molding die having a molding cavity and at least two runners connected to the molding cavity; (B) closing and clamping the molding die in a manner that the chips are located in the molding cavity thereof; (C) transferring a molding compound into the molding cavity wherein each chip is arranged in a manner that the two lines of bonding pads thereof are substantially perpendicular to the flowing direction of the molding compound; (D) curing the molding compound; and (E) unclamping and opening the molding die to take out the molded product.

Abstract translation: 一种用于BGA半导体芯片封装的模制方法，其包括支撑形成在其两侧的两行接合焊盘的芯片阵列的衬底。 成型方法包括以下步骤：（A）提供模制设备，其包括具有模制腔的模制模具和连接到模腔的至少两个浇道; （B）以芯片位于其模腔内的方式封闭和夹紧模具; （C）将模塑料转移到模制腔中，其中每个芯片以这样的方式排列，使得其两条接合焊盘基本上垂直于模塑料的流动方向; （D）固化模塑料; 和（E）松开和打开模具以取出模制产品。

公开(公告)号：US06312976B1

公开(公告)日：2001-11-06

申请号：US09444366

申请日：1999-11-22

Applicant: Chun Hung Lin ,  Chun-Chi Lee ,  Su Tao

Inventor： Chun Hung Lin ,  Chun-Chi Lee ,  Su Tao

IPC: H01L2144

CPC classification number: H01L21/565 ,  H01L23/49548 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct. The lower surface of each lead of the lead frame according to the present invention is smaller than the upper surface thereof such that each lead has a tapered profile which cooperates with the film to provide better sealing effect thereby preventing the formation of flash.

Abstract translation: 一种制造无引线半导体芯片封装的方法包括以下步骤：将半导体管芯附接到引线框架的管芯焊盘上，其中引线框架包括围绕管芯焊盘的周边布置的多个引线，并且每个引线具有缺口 形成在被打孔的位置; 将引线的内端引线接合到半导体管芯上的接合焊盘; 将薄膜吸附在成型模具的下部; 以半导体管芯位于成型模具的空腔中的方式封闭和夹紧成型模具，并且引线框架抵靠薄膜设置; 将可硬化的模塑料转移到所述空腔中; 硬化模塑料; 打开成型模具取出成型品; 沿着导线的切口冲压模制产品，从而使切割过程更方便正确。 根据本发明的引线框架的每个引线的下表面小于其上表面，使得每个引线具有与膜配合的锥形轮廓，以提供更好的密封效果，从而防止闪光的形成。

公开(公告)号：US06204559B1

公开(公告)日：2001-03-20

申请号：US09444365

申请日：1999-11-22

Applicant: Chun Hung Lin ,  Yire Zine Lee ,  Su Tao ,  Jian Wen Chen

Inventor： Chun Hung Lin ,  Yire Zine Lee ,  Su Tao ,  Jian Wen Chen

IPC: H01L2352

CPC classification number: H01L23/4985 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: This invention moves at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via provides sufficient supporting strength for the chip edge during molding process. Further, this invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. According to another aspect of this invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the copper mesh, offset via, the dummy via hole are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.

Abstract translation: 本发明将至少一个外部通孔向外移动到芯片边缘下方的位置，以形成偏移通孔。 由于通孔由铜制成，偏移通孔在成型过程中为芯片边缘提供足够的支撑强度。 此外，本发明还在没有通孔和迹线的区域上在基板上配置铜网，以增强用于支撑芯片的基板强度。 根据本发明的另一方面，在用于支撑芯片的芯片边缘下方的区域处为基板设置虚设通孔。 由于铜网，偏移通孔，虚拟通孔由具有足够的支撑强度的铜制成，因此可以消除模制过程中的裂纹问题。