发明授权
US06455376B1 Method of fabricating flash memory with shallow and deep junctions 有权
制造具有浅层和深层结的闪存的方法

  • 专利标题: Method of fabricating flash memory with shallow and deep junctions
  • 专利标题(中): 制造具有浅层和深层结的闪存的方法
  • 申请号: US09874455
    申请日: 2001-06-05
  • 公开(公告)号: US06455376B1
    公开(公告)日: 2002-09-24
  • 发明人: Tso Hung FanWen-Jer TsaiTao-Cheng Lu
  • 申请人: Tso Hung FanWen-Jer TsaiTao-Cheng Lu
  • 优先权: TW9016862 20010323
  • 主分类号: H01L218247
  • IPC分类号: H01L218247
Method of fabricating flash memory with shallow and deep junctions
摘要:
A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.
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