公开(公告)号：US06455376B1

公开(公告)日：2002-09-24

申请号：US09874455

申请日：2001-06-05

申请人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

摘要翻译： 公开了一种制造闪速存储器的方法。 该方法在衬底上开始堆叠栅极。 在其上已经形成有堆叠栅极的衬底上执行浅结掺杂，其中堆叠的栅极用作掩模，以便在与栅极的两侧相邻的衬底中形成浅结掺杂区域。 掩模层形成在衬底上以覆盖堆叠栅极的顶表面和侧壁，同时暴露浅结掺杂区域的部分。 在掩模层用作掩模的情况下，在衬底上进行深结掺杂以在衬底中邻近掩模层的两侧形成深结掺杂区域。 在去除掩模层之后，执行热处理以形成具有浅结掺杂区域和深掺杂区域的源极/漏极区域。