Method and system for data bus latency reduction using transfer size prediction for split bus designs

发明授权

US06457085B1 Method and system for data bus latency reduction using transfer size prediction for split bus designs 失效

标题翻译：用于分流总线设计的传输大小预测的数据总线延迟降低的方法和系统

请登陆查看更多内容

专利标题： Method and system for data bus latency reduction using transfer size prediction for split bus designs
专利标题（中）： 用于分流总线设计的传输大小预测的数据总线延迟降低的方法和系统
申请号： US09434764

申请日： 1999-11-04
公开(公告)号： US06457085B1

公开(公告)日： 2002-09-24
发明人: Praveen S. Reddy
申请人： Praveen S. Reddy
主分类号： G06F1338
IPC分类号： G06F1338

Method and system for data bus latency reduction using transfer size prediction for split bus designs

摘要：

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, functionality for address paths and data paths are implemented in the node controller and are implemented in physically separate components. Commands are sent from the node address controller to the node data controller to control the flow of data through a node.

摘要（中）：

提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备。节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。由于可能由大型总线引起的引脚限制，地址路径和数据路径的功能在节点控制器中实现，并且在物理上分离的组件中实现。命令从节点地址控制器发送到节点数据控制器，以控制通过节点的数据流。

信息查询

Espacenet