A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.