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    Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask
    3.
    发明授权
    Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask 有权
    使用交替的相移掩模对具有线和间隔阵列的掩模级的单次曝光

    公开(公告)号：US07413833B2

    公开(公告)日：2008-08-19

    申请号：US10846275

    申请日：2004-05-14

    Applicant: Shahid Butt ,  Scott Bukofsky ,  Ramachandra Divakaruni ,  Carl Radens ,  Wayne Ellis

    Inventor： Shahid Butt ,  Scott Bukofsky ,  Ramachandra Divakaruni ,  Carl Radens ,  Wayne Ellis

    IPC: G03F1/00

    CPC classification number: G03F1/30 ,  H01L21/3083 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10882

    Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated. At the opposite end of the array, the lines that have the opposite phase shift extend into the support region, and the lines of having the respective phase shift are terminated.

    Abstract translation: 使用替代的相移掩模，通过单次曝光在深沟槽图案之上形成有源区域图案。 为了防止相对相位的相邻空间在有源区域图案的基本不透明特征的端部彼此相交，使用一个或多个连接器来连接基本不透明图案的端部。 深沟槽图案的沟槽区域布置成使得连接器的传导路径被中断，并且防止线路彼此短路。 或者，使用交替相移掩模以单次曝光印刷具有线和间隔阵列的位线图案或字线图案和支撑区域。 在阵列区域的一端，具有各自的相移的线延伸到支撑区域，并且相反相移的线路终止。 在阵列的相对端，具有相反相移的线延伸到支撑区域中，并且具有相应相移的线路终止。

    Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask
    5.
    发明申请
    Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask 有权
    使用交替的相移掩模对具有线和间隔阵列的掩模级的单次曝光

    公开(公告)号：US20050255387A1

    公开(公告)日：2005-11-17

    申请号：US10846275

    申请日：2004-05-14

    Applicant: Shahid Butt ,  Scott Bukofsky ,  Ramachandra Divakaruni ,  Carl Radens ,  Wayne Ellis

    Inventor： Shahid Butt ,  Scott Bukofsky ,  Ramachandra Divakaruni ,  Carl Radens ,  Wayne Ellis

    IPC: G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/02

    CPC classification number: G03F1/30 ,  H01L21/3083 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10882

    Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated. At the opposite end of the array, the lines that have the opposite phase shift extend into the support region, and the lines of having the respective phase shift are terminated.

    Abstract translation: 使用替代的相移掩模，通过单次曝光在深沟槽图案之上形成有源区域图案。 为了防止相对相位的相邻空间在有源区域图案的基本不透明特征的端部彼此相交，使用一个或多个连接器来连接基本不透明图案的端部。 深沟槽图案的沟槽区域布置成使得连接器的传导路径被中断，并且防止线路彼此短路。 或者，使用交替相移掩模以单次曝光印刷具有线和间隔阵列的位线图案或字线图案和支撑区域。 在阵列区域的一端，具有相应相移的线延伸到支撑区域，并且相反相移的线路终止。 在阵列的相对端，具有相反相移的线延伸到支撑区域中，并且具有相应相移的线路终止。

    Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits
    6.
    发明授权
    Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits 失效
    用于提高非常大规模集成电路的测试，产量和性能的方法和装置

    公开(公告)号：US06320803B1

    公开(公告)日：2001-11-20

    申请号：US09533226

    申请日：2000-03-23

    Applicant: Martin Gall ,  Wayne Ellis ,  Shinji Miyamoto ,  Masahiro Yoshihara

    Inventor： Martin Gall ,  Wayne Ellis ,  Shinji Miyamoto ,  Masahiro Yoshihara

    IPC: G11C700

    CPC classification number: G01R31/31724 ,  G01R31/3187 ,  G01R31/31917 ,  G11C29/26

    Abstract: There is provided method and apparatus for improving and making more effective the testing of very large scale integrated (VLSI) devices such as a synchronous random access memory (SDRAM), along with improving their performance and their yield in production. The method includes the steps of providing a VLSI device with switching circuitry which permits respective arrays or banks of the device to be tested alone or simultaneously with separate sequences of test mode signals to identify defects, interactions and unwanted limitations in the overall performance of the device; using the information thus obtained to modify the test mode signals and where indicated the design of the device; iterating the previous steps to optimize a test methodology for the device; and using the optimized test methodology during burn-in of production devices. Logic circuitry is added to a VLSI device to facilitate the improved testing capability.

    Abstract translation: 提供了用于改进和更有效地测试诸如同步随机存取存储器（SDRAM）的大规模集成（VLSI）设备的方法和装置，同时提高其性能和生产成本。 该方法包括以下步骤：为VLSI设备提供切换电路，其允许单独或同时测试设备的相应阵列或同时测试模式信号的单独序列，以识别设备的整体性能中的缺陷，相互作用和不期望的限制 ; 使用如此获得的信息来修改测试模式信号，并且指示设备的设计; 迭代以前的步骤来优化设备的测试方法; 并在生产设备烧录期间使用优化的测试方法。 逻辑电路被添加到VLSI设备，以便于改进的测试能力。

    SRAM voltage control for improved operational margins
    8.
    发明申请
    SRAM voltage control for improved operational margins 有权

    公开(公告)号：US20080089116A1

    公开(公告)日：2008-04-17

    申请号：US11998948

    申请日：2007-12-03

    Applicant: Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    Inventor： Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C5/14 ,  G11C11/413

    Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

    SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
    10.
    发明申请
    SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS 有权
    用于改进操作标准的SRAM电压控制

    公开(公告)号：US20070121370A1

    公开(公告)日：2007-05-31

    申请号：US11164556

    申请日：2005-11-29

    Applicant: Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    Inventor： Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    IPC: G11C11/00

    CPC classification number: G11C5/14 ,  G11C11/413

    Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

    Abstract translation: 提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。 阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。 多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。 选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

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