发明授权
- 专利标题: Method of improving the planarization of wiring by CMP
- 专利标题(中): 通过CMP改善布线平面化的方法
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申请号: US09435612申请日: 1999-11-08
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公开(公告)号: US06465354B1公开(公告)日: 2002-10-15
- 发明人: Kazumi Sugai , Nobukazu Ito , Hiroaki Tachibana
- 申请人: Kazumi Sugai , Nobukazu Ito , Hiroaki Tachibana
- 优先权: JP10-319371 19981110
- 主分类号: H01L2144
- IPC分类号: H01L2144
摘要:
A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of ‘Erosion’ to be prevented, as well as it is capable of being prevented occurrence of ‘micro-scratch’ on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.
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