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21 条记录 (耗时 0.018 秒)

    Method of improving the planarization of wiring by CMP
    4.
    发明授权
    Method of improving the planarization of wiring by CMP 失效
    通过CMP改善布线平面化的方法

    公开(公告)号：US06465354B1

    公开(公告)日：2002-10-15

    申请号：US09435612

    申请日：1999-11-08

    申请人： Kazumi Sugai ,  Nobukazu Ito ,  Hiroaki Tachibana

    发明人： Kazumi Sugai ,  Nobukazu Ito ,  Hiroaki Tachibana

    IPC分类号： H01L2144

    CPC分类号： H01L21/2885 ,  H01L21/7684 ,  H01L21/76877

    摘要： A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of ‘Erosion’ to be prevented, as well as it is capable of being prevented occurrence of ‘micro-scratch’ on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.

    摘要翻译： 包括布线致密部分和布线隔离部分的半导体器件的制造方法能够防止“侵蚀”的发生，并且能够防止在氧化物层的表面上发生“微划痕”。 在形成由铜组成的金属镀层之前，制造方法在绝缘层上设置多个沟槽部分以嵌入沟槽部分。 制造工序以布线致密部中的金属镀层的粒径变得小于配线隔离部的晶粒尺寸的方式进行退火。 例如，退火的基板温度为70〜200℃。随后，制造步骤在抛光金属镀层的同时使半导体器件完美化，使基板的表面平坦。

    Method of forming a semiconductor device
    5.
    发明授权
    Method of forming a semiconductor device 失效
    形成半导体器件的方法

    公开(公告)号：US06372114B1

    公开(公告)日：2002-04-16

    申请号：US09288265

    申请日：1999-04-08

    申请人： Nobukazu Ito

    发明人： Nobukazu Ito

    IPC分类号： C25D502

    CPC分类号： H01L21/76873 ,  C23C14/042 ,  C23C14/50 ,  C23C14/568 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2855 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76843

    摘要： A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal of the metal seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

    摘要翻译： 一种在绝缘层上形成多层结构的方法包括以下步骤：通过使用第一沉积掩模在绝缘层的预定区域上选择性地沉积阻挡层; 通过使用第二沉积掩模选择性地沉积由物质与阻挡层不同的金属制成的金属种子层，使得金属种子层不仅在阻挡层的整个表面上延伸，而且延伸到位于 在绝缘层的预定区域之外; 以及形成由所述金属种子层的金属制成的金属镀层，使得所述金属镀层附着在所述金属种子层上，由此所述金属镀层与所述阻挡层以及所述绝缘层分离。

    Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface
    6.
    发明授权
    Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface 失效
    在暴露的铜表面形成多层铜互连形成铜氧化物的方法

    公开(公告)号：US06309970B1

    公开(公告)日：2001-10-30

    申请号：US09385756

    申请日：1999-08-30

    申请人： Nobukazu Ito ,  Yoshihisa Matsubara

    发明人： Nobukazu Ito ,  Yoshihisa Matsubara

    IPC分类号： H01L2144

    CPC分类号： H01L21/76888 ,  H01L21/321 ,  H01L21/76807 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/976 ,  H01L2924/00

    摘要： There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

    摘要翻译： 提出了包括多层铜互连的半导体器件; 其中对应于另一铜互连层的至少一个下层的铜互连的表面通过以20nm /次要的较小的氧化速率进行氧化而变成氧化铜至30nm或更大的厚度，从而反射 在通过光刻法形成沟槽以形成通过镶嵌形成铜互连的情况下，防止来自下级铜互连的曝光光。

    Method of forming a semiconductor device and an improved deposition system
    8.
    发明授权
    Method of forming a semiconductor device and an improved deposition system 失效
    形成半导体器件和改进的沉积系统的方法

    公开(公告)号：US06512281B2

    公开(公告)日：2003-01-28

    申请号：US09919389

    申请日：2001-07-31

    申请人： Nobukazu Ito

    发明人： Nobukazu Ito

    IPC分类号： H01L27095

    CPC分类号： H01L21/76873 ,  C23C14/042 ,  C23C14/50 ,  C23C14/568 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2855 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76843

    摘要： A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the same metal as the seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

    摘要翻译： 一种在绝缘层上形成多层结构的方法包括以下步骤：通过使用第一沉积掩模在绝缘层的预定区域上选择性地沉积阻挡层; 通过使用第二沉积掩模选择性地沉积由物质与阻挡层不同的金属制成的金属种子层，使得金属种子层不仅在阻挡层的整个表面上延伸，而且延伸到位于 在绝缘层的预定区域之外; 并且形成与种子层相同的金属制成的金属镀层，使得金属镀层附着在金属种子层上，由此金属镀层与阻挡层以及绝缘层分离。