When a CPU begins to monitor whether delay variation characteristics of a pulse width variation circuit have varied, it selects a basic delay setting value in a basic delay value setting block from a smallest one. The CPU sets a division number in a phase select block from a given minimum desired division number for pulse width modulation. The CPU senses the level of a phase comparison result signal (PHASE) from the pulse width modulation circuit. If the phase comparison result signal is stable at “1”, the CPU 1 fixes the division number. If the phase comparison result signal is “0” and the division number is not maximum, the CPU increases the division number and goes back to the setting of the division number. If the division number is maximum, the CPU increases the basic delay and goes back to the basic delay setting.