发明授权
- 专利标题: Ladder type clock network for reducing skew of clock signals
- 专利标题(中): 梯形时钟网络,用于减少时钟信号的偏移
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申请号: US09864190申请日: 2001-05-25
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公开(公告)号: US06483364B2公开(公告)日: 2002-11-19
- 发明人: Young-don Choi , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
- 申请人: Young-don Choi , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
- 优先权: KR2000-55204 20000920
- 主分类号: G06F104
- IPC分类号: G06F104
摘要:
A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.
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