公开(公告)号：US06556049B2

公开(公告)日：2003-04-29

申请号：US09805210

申请日：2001-03-14

申请人： Yi-do Koo ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Yi-do Koo ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： H03K190175

CPC分类号： H03K19/00384 ,  H03K19/00361

摘要： An output driver supplying constant output current regardless of output voltage changes. The output driver includes a current source for regulating changes in a voltage of an output terminal responsive to a reference signal, and an output current compensator that responds to the current source to supply constant current to the terminal. The current source includes a first MOS transistor having a drain coupled to the terminal and a gate to which the reference signal is input, and a second MOS transistor having a drain coupled to a source of the first MOS transistor, a gate to which data is input, and a source coupled to ground. The current source may be an open drain current source. The output current compensator includes a current compensator coupled to the terminal, and a sensing driver for sensing voltage changes of the terminal and driving the current compensator.

公开(公告)号：US06535040B2

公开(公告)日：2003-03-18

申请号：US09929522

申请日：2001-08-14

申请人： Yeon-jae Jung ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Yeon-jae Jung ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

摘要翻译： 占空比校正电路包括占空比校正器和检测电路。 占空比校正器响应于第一检测信号和具有第一占空比的第一控制信号产生具有比第一占空比更高的等效程度的第二占空比的第一输入信号。 检测电路响应于第一输入信号产生第一检测信号。 检测电路包括具有第一和第二电流源的电流源和电耦合到第一和第二电流源的偏置电路，并响应于第一输入信号控制第一和第二电流源的偏置。

公开(公告)号：US06483364B2

公开(公告)日：2002-11-19

申请号：US09864190

申请日：2001-05-25

申请人： Young-don Choi ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Young-don Choi ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： G06F104

CPC分类号： H03K5/15013 ,  G06F1/10 ,  H03K5/135

摘要： A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.

摘要翻译： 提供了一种用于减少时钟信号偏斜的梯形时钟网络。 时钟网络包括用于缓冲时钟信号的缓冲器，用于将第一缓冲器的输出延迟设定时间的第一延迟单元，连接到第一延迟单元的相应输出的第二缓冲器，以及连接到第一延迟单元的相应输出的第二延迟单元 第二缓冲区。 第一延迟单元和第二延迟单元基本上由时钟信号传播的线路的电阻和电容组成。 因此，内部时钟信号的偏斜减小，并且产生相对于半导体器件制造工艺，温度和电源电压的变化具有稳定占空比的内部时钟信号。

公开(公告)号：US06456122B1

公开(公告)日：2002-09-24

申请号：US09899223

申请日：2001-07-06

申请人： Joon-young Park ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Joon-young Park ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： G11C706

CPC分类号： H03K3/35613 ,  H03K5/2481 ,  H03K19/01721 ,  H03K19/018528

摘要： An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an “on” state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.

摘要翻译： 一种用于将伪差分输入信号变换为全差分输出信号的输入缓冲电路，其中，输入缓冲电路包括上拉电流源，两个下拉电流源，差分输入部分和正反馈部分。 上拉电流源由总是处于“导通”状态的两个PMOS晶体管形成，并且提供电流。 两个下拉电流源各自由NMOS晶体管形成，它们总是处于导通状态，并且吸收上拉电流。 差分输入部分由两个NMOS晶体管构成，分别接收输入信号和参考信号。 正反馈部分由两个NMOS晶体管形成，并且使用正反馈放大输入电路的两个输出端之间的电压差。

公开(公告)号：US06377093B1

公开(公告)日：2002-04-23

申请号：US09552424

申请日：2000-04-19

申请人： Dong-yun Lee ,  Kee-wook Jung

发明人： Dong-yun Lee ,  Kee-wook Jung

IPC分类号： H03L700

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0814 ,  H03L7/087

摘要： An integrated circuit having a locking circuit and method using the same are provided. The locking circuit includes a time-to-digital converter. The time-to-digital converter includes first and second delay chains, each for delaying one of two input signals at predetermined intervals. The time-to-digital converter also includes first and second phase comparators, each for comparing the delayed signal with the other signal and generating a digital signal. The locking circuit converts the phase difference between a feedback signal and an internal clock signal into a delay control signal group using the time-to-digital converter. The delay control signal group controls the delay time of a mirror delay circuit to rapidly minimize the phase difference between the feedback signal and the internal clock signal.

摘要翻译： 提供一种具有锁定电路的集成电路及其使用方法。 锁定电路包括时间 - 数字转换器。 时间 - 数字转换器包括第一和第二延迟链，每个延迟链用于以预定间隔延迟两个输入信号之一。 时间 - 数字转换器还包括第一和第二相位比较器，每个用于将延迟信号与另一信号进行比较并产生数字信号。 锁定电路使用时间 - 数字转换器将反馈信号和内部时钟信号之间的相位差转换成延迟控制信号组。 延迟控制信号组控制反射镜延迟电路的延迟时间，以快速最小化反馈信号和内部时钟信号之间的相位差。