A test circuit tests for defective memory cells in a memory portion of an Embedded DRAM. The Embedded DRAM includes an array of memory cells. The test circuit includes a test mode terminal adapted to receive a test mode signal and a plurality of comparison circuits. Each comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each comparison circuit compares the binary values of the read and expect data signals and develops and inactive error signal on an output when the compared signals have the same binary values, and develops an active error signal when the compared signals have different binary values. A storage circuit is coupled to the outputs of the comparison circuits. The storage circuit latches the error signals output by the comparison circuits and sequentially transfers the latched error signals onto a data terminal of the Embedded DRAM. A test control circuit is coupled to the comparison circuits, the test mode termninal, and the storage circuit. The test control circuit operates when the test mode signal is active, to apply data from addressed memory cells respectively on the first inputs of the comparison circuits. The test control circuit also applies respective expect data on the second inputs of the comparison circuits and controls the storage circuit to latch the resulting error signals and thereafter sequentially transfer the latched error signals onto the data terminal. The test circuit may include additional stages of comparison circuits to further compress read test data, as well as additional storage circuits for storing such additional compressed data.