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    Method and apparatus for testing an embedded DRAM
    1.
    发明授权
    Method and apparatus for testing an embedded DRAM 有权
    用于测试嵌入式DRAM的方法和装置

    公开(公告)号：US06484278B1

    公开(公告)日：2002-11-19

    申请号：US09573074

    申请日：2000-05-16

    申请人： Todd A. Merritt ,  Donald M. Morgan ,  Huy Thanh Vo

    发明人： Todd A. Merritt ,  Donald M. Morgan ,  Huy Thanh Vo

    IPC分类号： G11C2900

    CPC分类号： G11C29/14

    摘要： A test circuit tests for defective memory cells in a memory portion of an Embedded DRAM. The Embedded DRAM includes an array of memory cells. The test circuit includes a test mode terminal adapted to receive a test mode signal and a plurality of comparison circuits. Each comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each comparison circuit compares the binary values of the read and expect data signals and develops and inactive error signal on an output when the compared signals have the same binary values, and develops an active error signal when the compared signals have different binary values. A storage circuit is coupled to the outputs of the comparison circuits. The storage circuit latches the error signals output by the comparison circuits and sequentially transfers the latched error signals onto a data terminal of the Embedded DRAM. A test control circuit is coupled to the comparison circuits, the test mode termninal, and the storage circuit. The test control circuit operates when the test mode signal is active, to apply data from addressed memory cells respectively on the first inputs of the comparison circuits. The test control circuit also applies respective expect data on the second inputs of the comparison circuits and controls the storage circuit to latch the resulting error signals and thereafter sequentially transfer the latched error signals onto the data terminal. The test circuit may include additional stages of comparison circuits to further compress read test data, as well as additional storage circuits for storing such additional compressed data.

    摘要翻译： 测试电路测试嵌入式DRAM的存储器部分中的有缺陷的存储单元。 嵌入式DRAM包括一组存储单元。 测试电路包括适于接收测试模式信号的测试模式终端和多个比较电路。 每个比较电路包括适于接收读取数据信号的第一输入和适于接收期望数据信号的第二输入。 每个比较电路比较读取和期望数据信号的二进制值，并且当比较的信号具有相同的二进制值时，在输出上产生和无效的误差信号，并且当比较的信号具有不同的二进制值时产生有效的误差信号。 存储电路耦合到比较电路的输出端。 存储电路锁存由比较电路输出的误差信号，并将锁存的误差信号依次传送到嵌入式DRAM的数据端。 测试控制电路耦合到比较电路，测试模式termninal和存储电路。 当测试模式信号有效时，测试控制电路工作，分别将来自寻址的存储器单元的数据应用于比较电路的第一输入端。 测试控制电路还对比较电路的第二输入端施加各自的期望数据，并且控制存储电路以锁存所得到的误差信号，然后将锁存的误差信号顺序地传送到数据终端。 测试电路可以包括用于进一步压缩读取测试数据的另外的比较电路级，以及用于存储这种附加压缩数据的附加存储电路。

    Method and apparatus for testing embedded DRAM
    2.
    发明授权
    Method and apparatus for testing embedded DRAM 有权
    用于测试嵌入式DRAM的方法和装置

    公开(公告)号：US6072737A

    公开(公告)日：2000-06-06

    申请号：US130632

    申请日：1998-08-06

    申请人： Donald M. Morgan ,  Huy Thanh Vo

    发明人： Donald M. Morgan ,  Huy Thanh Vo

    IPC分类号： G11C29/14 ,  G11C7/00

    CPC分类号： G11C29/14

    摘要： A test circuit tests for defective memory cells in a memory portion of an Embedded DRAM. The Embedded DRAM includes an array of memory cells. The test circuit includes a test mode terminal adapted to receive a test mode signal and a plurality of comparison circuits. Each comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each comparison circuit compares the binary values of the read and expect data signals and develops and inactive error signal on an output when the compared signals have the same binary values, and develops an active error signal when the compared signals have different binary values. A storage circuit is coupled to the outputs of the comparison circuits. The storage circuit latches the error signals output by the comparison circuits and sequentially transfers the latched error signals onto a data terminal of the Embedded DRAM. A test control circuit is coupled to the comparison circuits, the test mode terminal, and the storage circuit. The test control circuit operates when the test mode signal is active, to apply data from addressed memory cells respectively on the first inputs of the comparison circuits. The test control circuit also applies respective expect data on the second inputs of the comparison circuits and controls the storage circuit to latch the resulting error signals and thereafter sequentially transfer the latched error signals onto the data terminal. The test circuit may include additional stages of comparison circuits to further compress read test data, as well as additional storage circuits for storing such additional compressed data.

    摘要翻译： 测试电路测试嵌入式DRAM的存储器部分中的有缺陷的存储单元。 嵌入式DRAM包括一组存储单元。 测试电路包括适于接收测试模式信号的测试模式终端和多个比较电路。 每个比较电路包括适于接收读取数据信号的第一输入和适于接收期望数据信号的第二输入。 每个比较电路比较读取和期望数据信号的二进制值，并且当比较的信号具有相同的二进制值时，在输出上产生和无效的误差信号，并且当比较的信号具有不同的二进制值时产生有效的误差信号。 存储电路耦合到比较电路的输出端。 存储电路锁存由比较电路输出的误差信号，并将锁存的误差信号依次传送到嵌入式DRAM的数据端。 测试控制电路耦合到比较电路，测试模式终端和存储电路。 当测试模式信号有效时，测试控制电路工作，分别将来自寻址的存储器单元的数据应用于比较电路的第一输入端。 测试控制电路还对比较电路的第二输入端施加各自的期望数据，并且控制存储电路以锁存所得到的误差信号，然后将锁存的误差信号顺序地传送到数据终端。 测试电路可以包括用于进一步压缩读取测试数据的另外的比较电路级，以及用于存储这种附加压缩数据的附加存储电路。

    Device and method to reduce wordline RC time constant in semiconductor memory devices
    5.
    发明授权
    Device and method to reduce wordline RC time constant in semiconductor memory devices 有权

    公开(公告)号：US07570504B2

    公开(公告)日：2009-08-04

    申请号：US09808750

    申请日：2001-03-15

    申请人： Huy Thanh Vo

    发明人： Huy Thanh Vo

    IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C8/00

    CPC分类号： G11C8/14 ,  G11C5/063

    摘要： A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that produces a device with a lower RC time constant than devices formed using prior art techniques. In one embodiment of the invention low resistivity metal strapping layers are attached to alternating halves of wordlines in a single memory array. The alternating pattern allows the low resistivity of the strapping layers to be utilized without introducing significant negative capacitive resistance effects due to strapping layers being too close to each other.

    Threshold voltage scalable buffer with reference level
    6.
    发明授权
    Threshold voltage scalable buffer with reference level 失效
    具有参考电平的阈值电压可伸缩缓冲器

    公开(公告)号：US06323685B1

    公开(公告)日：2001-11-27

    申请号：US09361455

    申请日：1999-07-27

    申请人： Huy Thanh Vo

    发明人： Huy Thanh Vo

    IPC分类号： H03K5153

    CPC分类号： H03K19/018521 ,  H03K19/0016

    摘要： A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

    摘要翻译： 缓冲电路（10）。 缓冲电路（10）包括具有限制第一逆变器（12）使用的待机电流的第一限流器（18）的第一逆变器（12）。 此外，缓冲电路（10）包括耦合到第一反相器（12）的输出的第二反相器（14）。 输入缓冲器（10）将提供给第一反相器（12）的输入信号的第一逻辑电平转换为第二反相器（14）的输出处的第二逻辑电平。 缓冲电路（10）还包括耦合在第一和第二反相器（12和14）之间的第二限流电路（16），以进一步限制缓冲电路（10）中的待机电流。

    Threshold voltage scalable buffer with reference level
    7.
    发明授权
    Threshold voltage scalable buffer with reference level 失效
    具有参考电平的阈值电压可伸缩缓冲器

    公开(公告)号：US5703500A

    公开(公告)日：1997-12-30

    申请号：US648443

    申请日：1996-05-15

    申请人： Huy Thanh Vo

    发明人： Huy Thanh Vo

    IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K19/0948

    CPC分类号： H03K19/018521 ,  H03K19/0016

    摘要： A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

    摘要翻译： 缓冲电路（10）。 缓冲电路（10）包括具有限制第一逆变器（12）使用的待机电流的第一限流器（18）的第一逆变器（12）。 此外，缓冲电路（10）包括耦合到第一反相器（12）的输出端的第二反相器（14）。 输入缓冲器（10）将提供给第一反相器（12）的输入信号的第一逻辑电平转换为第二反相器（14）的输出处的第二逻辑电平。 缓冲电路（10）还包括耦合在第一和第二反相器（12和14）之间的第二限流电路（16），以进一步限制缓冲电路（10）中的待机电流。

    System for testing integrated circuit devices
    8.
    发明授权
    System for testing integrated circuit devices 失效
    集成电路设备测试系统

    公开(公告)号：US06496027B1

    公开(公告)日：2002-12-17

    申请号：US08916994

    申请日：1997-08-21

    申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    IPC分类号： G01R3102

    CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

    摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

    摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

    Method and apparatus for timing control in a memory device
    9.
    发明授权
    Method and apparatus for timing control in a memory device 失效
    用于存储器件中定时控制的方法和装置

    公开(公告)号：US5663925A

    公开(公告)日：1997-09-02

    申请号：US581472

    申请日：1995-12-18

    申请人： Huy Thanh Vo

    发明人： Huy Thanh Vo

    IPC分类号： G11C7/14 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/14 ,  G11C8/18

    摘要： In a memory device such as a DRAM or multiport DRAM, each of a plurality of memory cells includes an access transistor with a gate connected to a word line and a storage capacitor with a storage node connected through the access transistor to a digit line. Data is transferred on the digit line to and from the storage capacitor when the word line is activated and the access transistor enabled thereby. According to the present invention, a timing control circuit is provided to control deactivation of the word line. The timing control circuit includes a digit-write/transfer model that simulates a read-write cycle in a DRAM or a serial write transfer operation in a multiport DRAM. The digit-write transfer model produces an output signal indicating the state of the modeled data transfer operation. The timing control circuit also includes a reference voltage circuit and a level comparator. The level comparator compares the model output signal to the reference voltage provided by the reference voltage circuit. The level comparator includes a sensitive analog multi-stage current mirror differential amplifier circuit and produces a signal input to a RAS timing chain circuit which deactivates the word line upon completion of the modeled data transfer operation.

    摘要翻译： 在诸如DRAM或多端口DRAM的存储器件中，多个存储器单元中的每一个包括具有连接到字线的栅极的存取晶体管和具有通过存取晶体管连接到数字线的存储节点的存储电容器。 当字线被激活并且由此启用存取晶体管时，数据在存储电容器的数字线上被传送到存储电容器。 根据本发明，提供一种定时控制电路来控制字线的去激活。 定时控制电路包括模拟DRAM中的读写周期或多端口DRAM中的串行写传输操作的数字写/传输模型。 数位写传输模型产生一个指示建模数据传输操作状态的输出信号。 定时控制电路还包括参考电压电路和电平比较器。 电平比较器将模型输出信号与参考电压电路提供的参考电压进行比较。 电平比较器包括灵敏的模拟多级电流镜差分放大器电路，并且产生对RAS定时链电路的信号输入，其在建模的数据传送操作完成时停用字线。