- 专利标题： Logic circuit and its forming method
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申请号： US10122385申请日： 2002-04-16
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公开(公告)号： US06486708B2公开(公告)日： 2002-11-26
- 发明人: Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
- 申请人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
- 优先权： JP9-327536 19971128
- 主分类号： H03K19094
- IPC分类号： H03K19094
摘要：
This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).
公开/授权文献
- US20020149394A1 Logic circuit and its forming method 公开/授权日：2002-10-17