公开(公告)号：US06798249B2

公开(公告)日：2004-09-28

申请号：US10303974

申请日：2002-11-26

Applicant: Tak Ying Wong ,  David Ho ,  Wee Teck Lee ,  Khim Leng Low

Inventor： Tak Ying Wong ,  David Ho ,  Wee Teck Lee ,  Khim Leng Low

IPC: H03K19094

CPC classification number: H03K3/356139

Abstract: A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.

Abstract translation: 电流模式逻辑（CML）触发器包括第一CML锁存器和第二CML锁存器。 多个上拉开关响应于复位信号。 第一和第二CML锁存器的输出通过上拉开关上拉至电源电压。 第一个CML锁存器包括由复位信号驱动的用于复位锁存器的第一上拉隔离开关。

公开(公告)号：US06717440B2

公开(公告)日：2004-04-06

申请号：US10357647

申请日：2003-02-04

Applicant: Donald M. Morgan

Inventor： Donald M. Morgan

IPC: H03K19094

CPC classification number: H04L25/242 ,  H03K19/01707

Abstract: Systems and methods are provided for improving signal propagation. A repeater segments a transmission line into a first and a second line. The repeater includes an inverting amplifier and an equilibration circuit. The inverting amplifier has an input connected to the first line and an output connected to the second line. The amplifier receives and an input signal at a first logic potential and transmits an output signal at an inverted second logic potential during and an active portion of a cycle. The equilibration circuit electrically isolates the first line and the second line and shorts the first line to the second line during and an inactive portion of the cycle. Upon completion of the inactive portion of the cycle, the first line and the second line have substantially equal starting potentials between the first logic potential and the second logic potential. Setting the starting potential between the first and second logic potentials shortens the delay associated with a transition between logic potentials. Additionally, one embodiment of the equilibration circuit selectively disconnects the amplifier from the power rails.

Abstract translation: 提供了用于改善信号传播的系统和方法。 中继器将传输线分割成第一和第二行。 中继器包括反相放大器和平衡电路。 反相放大器具有连接到第一线路的输入端和连接到第二线路的输出端。 放大器接收第一逻辑电位的输入信号，并在循环的有效部分期间以反相的第二逻辑电位发送输出信号。 平衡电路将第一线路和第二线路电隔离，并在该周期的非活动部分期间将第一线路短路到第二线路。 在完成了该周期的无效部分之后，第一线路和第二线路具有在第一逻辑电位和第二逻辑电位之间具有基本相等的起始电位。 设置第一和第二逻辑电位之间的起始电位会缩短与逻辑电位之间的转换相关的延迟。 此外，平衡电路的一个实施例选择性地将放大器与电源轨分离。

公开(公告)号：US06700411B2

公开(公告)日：2004-03-02

申请号：US10234106

申请日：2002-09-05

Applicant: Katsuki Matsudera ,  Masaru Koyanagi

Inventor： Katsuki Matsudera ,  Masaru Koyanagi

IPC: H03K19094

CPC classification number: H03K19/0963 ,  H03K19/00315

Abstract: An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

公开(公告)号：US06696864B2

公开(公告)日：2004-02-24

申请号：US10266773

申请日：2002-10-09

Applicant: Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

Inventor： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC: H03K19094

CPC classification number: G06F17/505 ,  H03K19/1737

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract translation: 本申请提出了一种新的逻辑电路，包括第一选择器（S1），其中控制输入S由第一输入信号（IN1）控制，输入I1或I0由第二输入信号（IN2）控制，输出 O连接到第一节点（N1），并且第三选择器（S3），其中控制输入S由第一节点（N1）控制，输入I1由第三输入信号（IN3）控制，输入 I0由第一输入信号（IN1）控制，输出端连接到第一输出信号（OUT1）。

公开(公告)号：US06677780B2

公开(公告)日：2004-01-13

申请号：US10303841

申请日：2002-11-26

Applicant: Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

Inventor： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC: H03K19094

CPC classification number: H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract translation: 在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。 在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。 在升高电路中，提供逻辑运算功能。

公开(公告)号：US06628145B1

公开(公告)日：2003-09-30

申请号：US09792693

申请日：2001-02-23

Applicant: Douglas Sudjian

Inventor： Douglas Sudjian

IPC: H03K19094

CPC classification number: H03K19/01707 ,  H03K19/09432 ,  H03K23/667

Abstract: A logic gate that includes a first differential amplifier and a feedback circuit. The first differential amplifier has a number of first (e.g., non-inverting) inputs and a second (e.g., inverting) input, receives and senses input signals applied to the non-inverting inputs, and provides a differential output that is a particular logic function (e.g., an ‘OR’) of the input signals. The non-inverting inputs may correspond to the gates of a number of transistors coupled in parallel to form an OR function. The feedback circuit detects the (e.g., non-inverting node of the) differential output and provides a control signal for the inverting input of the first differential amplifier. The logic gate typically further includes a second differential amplifier that senses and further drives the differential output.

Abstract translation: 逻辑门，其包括第一差分放大器和反馈电路。 第一差分放大器具有多个第一（例如，非反相）输入和第二（例如，反相）输入，接收和感测施加到非反相输入的输入信号，并提供作为特定逻辑的差分输出 功能（例如，“OR”）。 非反相输入可以对应于并联耦合的多个晶体管的栅极以形成OR功能。 反馈电路检测差分输出的（例如，非反相节点），并为第一差分放大器的反相输入提供控制信号。 逻辑门通常还包括感测并进一步驱动差分输出的第二差分放大器。

公开(公告)号：US06624662B1

公开(公告)日：2003-09-23

申请号：US09608503

申请日：2000-06-30

Applicant: Andrew M. Volk

Inventor： Andrew M. Volk

IPC: H03K19094

CPC classification number: H03K19/0005 ,  H03K19/018585

Abstract: A compensating buffer providing both course tuning on initialization and fine-tuning during operation is disclosed. The course tuning is provided by a plurality of binary-weighted driver legs which are selected during initialization. The fine-tuning which is selectable during both initialization and during operation is provided through linear-weighted biasing. The linear-weighted biasing is simplified through the use of a digital-to-analog converter.

Abstract translation: 公开了一种在操作期间提供初始化和微调两个过程调整的补偿缓冲器。 课程调整由在初始化期间选择的多个二进制加权的驾驶员腿提供。 在初始化和运行期间均可选择的微调通过线性加权偏置来提供。 通过使用数模转换器来简化线性加权偏置。

公开(公告)号：US06624660B2

公开(公告)日：2003-09-23

申请号：US10010820

申请日：2001-12-06

Applicant: Wen Li ,  Michael D. Chaine ,  Manny Kin Ma

Inventor： Wen Li ,  Michael D. Chaine ,  Manny Kin Ma

IPC: H03K19094

CPC classification number: H03K19/00315

Abstract: An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.

Abstract translation: 一种用于半导体器件的输出驱动器电路。 在一个实施例中，输出驱动器耦合到半导体器件的输出端子，并且由形成在P型衬底中的N阱中的N沟道下拉晶体管和P沟道上拉晶体管组成。 形成在N阱中的结合区域通过去耦晶体管选择性地耦合到电源电位，并且在驱动器的正常操作期间维持N阱的电源电压偏置。 过驱动检测电路耦合到输出端子。 在检测出输出端子上的过驱动条件（例如超过预定最大值的电压）或注入输出端子（或两者）的过电流时，过驱动检测电路解除施加到去耦晶体管的栅极的控制信号， 从而将N阱与电源电位分离。 在一个实施例中，去耦晶体管不耦合到输出端。

公开(公告)号：US06586970B1

公开(公告)日：2003-07-01

申请号：US09953842

申请日：2001-09-17

Applicant: Chang Ho Jung

Inventor： Chang Ho Jung

IPC: H03K19094

CPC classification number: G11C8/10

Abstract: The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs are the same as the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate. This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.

Abstract translation: 本发明描述了在阶段之一中利用伪NAND或伪与门解码的多级解码器和方法。 本发明提供了一种解码器，包括具有两个或多个第一输入的第一级电路，其产生一个或多个第一输出; 以及具有至少一个第二输入和至少一个第二输出的第二级电路，其中所述一个或多个第一输出与所述至少一个第二输入相同，其中所述组中的至少一个包括第一级电路和 第二级电路包括伪与门或伪NAND门。 本发明提供了一种解码方法，包括以下步骤：响应于两个或更多个地址位产生一个信号，并通过产生的信号启用解码器。

公开(公告)号：US06522174B2

公开(公告)日：2003-02-18

申请号：US09835892

申请日：2001-04-16

Applicant: Aaron K. Martin ,  Stephen R. Mooney

Inventor： Aaron K. Martin ,  Stephen R. Mooney

IPC: H03K19094

CPC classification number: H04L25/0282 ,  H03K19/01721 ,  H03K19/018528 ,  H04L25/0272 ,  H04L25/0294

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.