发明授权
US06492856B1 Edge triggered latch with symmetrical paths from clock to data outputs
失效
边沿触发闩锁,具有从时钟到数据输出的对称路径
- 专利标题: Edge triggered latch with symmetrical paths from clock to data outputs
- 专利标题(中): 边沿触发闩锁,具有从时钟到数据输出的对称路径
-
申请号: US10145847申请日: 2002-05-14
-
公开(公告)号: US06492856B1公开(公告)日: 2002-12-10
- 发明人: Nobuo Kojima , Huajun Wen
- 申请人: Nobuo Kojima , Huajun Wen
- 主分类号: H03K312
- IPC分类号: H03K312
摘要:
A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.
公开/授权文献
信息查询