公开(公告)号：US06642764B2

公开(公告)日：2003-11-04

申请号：US10012779

申请日：2001-12-10

申请人： Alexander Roger Deas ,  Vasily Grigorievich Atyunin ,  Igor Anatolievich Abrosimov

发明人： Alexander Roger Deas ,  Vasily Grigorievich Atyunin ,  Igor Anatolievich Abrosimov

IPC分类号： H03K312

CPC分类号： H03K5/088

摘要： A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

公开(公告)号：US06549049B1

公开(公告)日：2003-04-15

申请号：US10120335

申请日：2002-04-11

申请人： Eugene Hinterscher

发明人： Eugene Hinterscher

IPC分类号： H03K312

CPC分类号： H03K3/3565

摘要： A differential pair input receiver (30) having variable reference voltages that may be customized by the designer so as to increase and decrease noise margins of the amplifier. This input receiver (30) includes a complementary self-biased differential amplifier (10) and a dynamic hysteresis voltage reference circuit (20), wherein the complementary self-biased differential amplifier (10) has an input node (Input2), a reference output node (S2), and a dynamic voltage reference node (VDYNREF). The dynamic hysteresis voltage reference circuit (20) connects between the reference output node (S2) and the dynamic voltage reference node (VDYNREF) to provide a reference voltage (Vref) at the dynamic voltage reference node(VDYNREF). The reference voltage (Vref) serves as a threshold for the complementary self-biased differential amplifier (10), such that the output transitions from high-to-low and low-to-high when the input is equal to the reference voltage (Vref). Furthermore, the dynamic hysteresis voltage reference circuit (20) adjusts the reference voltage (Vref) to provide a different threshold for each respective transition from high-to-low and from low-to-high.

摘要翻译： 差分对输入接收器（30）具有可由参考设计者定制的可变参考电压，以增加和减小放大器的噪声容限。 该输入接收器（30）包括互补自偏置差分放大器（10）和动态滞环电压参考电路（20），其中互补自偏置差分放大器（10）具有输入节点（Input2），参考输出 节点（S2）和动态电压参考节点（VDYNREF）。 动态滞环电压参考电路（20）在参考输出节点（S2）和动态电压参考节点（VDYNREF）之间连接，以在动态参考电压（VDYNREF）提供参考电压（Vref）。 参考电压（Vref）用作互补自偏置差分放大器（10）的阈值，使得当输入等于参考电压（Vref）时，输出从高电平变为低电平和低电平至高电平 ）。 此外，动态滞环电压参考电路（20）调节参考电压（Vref）以为从高到低和从低到高的每个相应转变提供不同的阈值。

公开(公告)号：US06448829B1

公开(公告)日：2002-09-10

申请号：US09876765

申请日：2001-06-07

申请人： Ritesh Saraf

发明人： Ritesh Saraf

IPC分类号： H03K312

CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/35625

摘要： A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of time after the start of the evaluation phase.

摘要翻译： 提供具有动态输入级和静态输出级的低保持时间触发器。 触发器在触发器的评估阶段期间使用反馈级来维持动态节点上的值，使得触发器的输入仅在开始之后必须保持相对较短的时间段 评估阶段。

公开(公告)号：US06377096B1

公开(公告)日：2002-04-23

申请号：US09696104

申请日：2000-10-24

申请人： Samuel D. Naffziger

发明人： Samuel D. Naffziger

IPC分类号： H03K312

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A static logic signal to dynamic logic interface that produces a monotonic output. An inverse of a dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and enable inputs. A delayed version of the inverse of the evaluate clock is generated by a delay element. The delayed inverse of the evaluate clock is fed to the enable input of the latch. The input to the latch comes from static logic and the output of the latch is fed to the dynamic logic. The net result is a latch that is open until the evaluate clock is instructing the dynamic logic to evaluate, and remains closed until a delay element delay time after the evaluate clock instructs the dynamic logic to reset.

摘要翻译： 静态逻辑信号到动态逻辑接口产生单调输出。 动态逻辑评估时钟的倒数被馈送到具有时钟和使能输入的透明锁存器的时钟输入。 延迟元件产生评估时钟的逆的延迟版本。 评估时钟的延迟反相被馈送到锁存器的使能输入。 锁存器的输入来自静态逻辑，锁存器的输出被馈送到动态逻辑。 净结果是一个锁存器，直到评估时钟指示动态逻辑进行评估，并且保持关闭，直到评估时钟指示动态逻辑复位后的延迟元件延迟时间为止。

公开(公告)号：US06750690B1

公开(公告)日：2004-06-15

申请号：US10350927

申请日：2003-01-22

申请人： Karl Edwards

发明人： Karl Edwards

IPC分类号： H03K312

CPC分类号： H03K3/012 ,  H03K3/2825 ,  H03K3/288

摘要： A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

摘要翻译： 提供高速，电流驱动的锁存器。 锁存器传导电流并包括输出，SET电路和RESET电路。 输出在第一状态和第二状态之间变化。 SET电路在第一状态下导通锁存器中存在的电流，使得SET电路保持接近将晶体管的输出从第一电平改变到第二电平所需的电平，并且RESET电路在 第二电平使得RESET电路接近将晶体管的输出从第二电平改变到第一电平所需的电平。

公开(公告)号：US06741111B1

公开(公告)日：2004-05-25

申请号：US10249581

申请日：2003-04-21

申请人： Ke Wu

发明人： Ke Wu

IPC分类号： H03K312

CPC分类号： H03K3/0372 ,  H03K3/012

摘要： A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.

摘要翻译： 缓冲芯片将数据向存储器模块上的存储器进行计时。 缓冲芯片上的寄存器或触发器的数据输入路径通过去除触发器的输入上的多路复用来加速。 加速数据输入路径可以减少功耗，因为可以使用较小的输入缓冲区。 控制逻辑组合芯片选择和数据选通控制输入，防止触发器的时钟。 控制逻辑输出组合的选通信号。 复位锁存器由组合的选通信号触发。 当芯片选择和数据选通输入均为活动时，置位复位锁存器允许时钟通过触发器。 设置复位锁存器阻止芯片选择和数据选通输入的上升转换从更改时钟到触发器，从而防止数据时钟错误。

公开(公告)号：US06621318B1

公开(公告)日：2003-09-16

申请号：US09872839

申请日：2001-06-01

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H03K312

CPC分类号： H03K3/0375 ,  H03K3/012 ,  H03K3/037

摘要： Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength, latches according to the invention include feedback stages with multiple inverters. By using only transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latches of the invention is increased significantly over that of prior art latches. One embodiment of the invention allows for minimum supply voltages of 85 millivolts, an improvement of over nine hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts,

摘要翻译： 低压锁存器被设计成使得包括在锁存器中的所有晶体管都是低阈值晶体管，并且低阈值晶体管具有相同的沟道尺寸，即相同的沟道长度和宽度。 为了满足这一要求并仍然提供足够强度的反馈信号，根据本发明的锁存器包括具有多个逆变器的反馈级。 通过仅使用本发明的锁存器中相同通道长度和宽度的晶体管，本发明的锁存器的电压可伸缩性比现有技术的锁存器显着增加。 与典型的现有技术的800毫伏的最小电压要求相比，本发明的一个实施例允许85毫伏的最小电源电压，超过百分之九十的改进，

公开(公告)号：US06608513B2

公开(公告)日：2003-08-19

申请号：US09820579

申请日：2001-03-28

申请人： James W. Tschanz ,  Siva G. Narendra ,  Vivek K. De

发明人： James W. Tschanz ,  Siva G. Narendra ,  Vivek K. De

IPC分类号： H03K312

CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/037

摘要： A pulse generator system includes a plurality of buffers at least two transmission gates. The inverters successively and input insert delays into an signal having a series of pulses, each pulse having first and second edges. The transmission gates are operatively coupled to the inverters. The first transmission gate selectively passes the input signal. The second transmission gape selectively passes inverted signal of the input signal.

摘要翻译： 脉冲发生器系统包括多个缓冲器，至少两个传输门。 反相器依次输入插入延迟到具有一系列脉冲的信号，每个脉冲具有第一和第二边缘。 传输门可操作地耦合到逆变器。 第一传输门选择性地传递输入信号。 第二传输gape选择性地通过输入信号的反相信号。

公开(公告)号：US06512406B1

公开(公告)日：2003-01-28

申请号：US09465437

申请日：1999-12-16

申请人： Charles E. Dike

发明人： Charles E. Dike

IPC分类号： H03K312

CPC分类号： H03K3/0375 ,  H03K3/356121

摘要： An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.

摘要翻译： 一种具有锁芯的装置，其中所述锁芯具有多个装置，并且所述装置中的至少一个具有背栅偏置网。 偏压电路耦合到背栅偏置网。 该装置还可以包括背对背反相器，其中每个反相器输出耦合到另一个反相器输入。 反相器还可以包括PFET晶体管和NFET晶体管，其中PFET晶体管具有背栅偏压网。 反相器还可以包括PFET晶体管和NFET晶体管，NFET晶体管具有背栅偏压网。 反相器还可以包括PFET晶体管和NFET晶体管，NFET晶体管和PFET晶体管具有背栅偏压网。 偏置电压电路还可以被配置为当亚稳态可能发生时施加偏置电压。 偏置电压电路还可以包括NAND门。

公开(公告)号：US06492856B1

公开(公告)日：2002-12-10

申请号：US10145847

申请日：2002-05-14

申请人： Nobuo Kojima ,  Huajun Wen

发明人： Nobuo Kojima ,  Huajun Wen

IPC分类号： H03K312

CPC分类号： H03K3/356121

摘要： A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

摘要翻译： 公开了一种新的D型锁存结构，其具有输入数据采样电路和对称交叉耦合锁存电路。 时钟通过逆变器电路延迟预定时间。 时钟和延迟反相时钟用于产生时钟窗口时间，在此期间，数据输入状态和反相数据输入状态在锁存输出和互补上被断言。 锁存器输出在每个输出电路级交叉耦合到上拉和下拉电路。 可以使用公共的下拉晶体管来进一步减少器件并改善从时钟到锁存器输出的路径延迟。 通过锁存器输出的交叉耦合反馈来增强对变化的锁存器输出的数据输入的状态的时钟窗口，以改善锁存器输出的差分转换定时。 D型锁存器具有更少的晶体管和更好的延迟，以及比现有技术设计更精确的转变偏移。