发明授权
US06495413B2 Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits
有权
用于屏蔽用于铁电存储器集成电路的特别实用的集成电容器的结构
- 专利标题: Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits
- 专利标题(中): 用于屏蔽用于铁电存储器集成电路的特别实用的集成电容器的结构
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申请号: US09797394申请日: 2001-02-28
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公开(公告)号: US06495413B2公开(公告)日: 2002-12-17
- 发明人: Shan Sun , George Hickert , Diana Johnson , John Ortega , Eric Dale , Masahisa Ueda
- 申请人: Shan Sun , George Hickert , Diana Johnson , John Ortega , Eric Dale , Masahisa Ueda
- 主分类号: H01L218242
- IPC分类号: H01L218242
摘要:
A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.
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