- 专利标题: DRAM cell configuration and fabrication method
-
申请号: US09951243申请日: 2001-09-12
-
公开(公告)号: US06504200B2公开(公告)日: 2003-01-07
- 发明人: Till Schlösser , Bernhard Sell , Josef Willer
- 申请人: Till Schlösser , Bernhard Sell , Josef Willer
- 优先权: DE19911148 19990312
- 主分类号: H01L27108
- IPC分类号: H01L27108
摘要:
Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.
公开/授权文献
- US20020079527A1 DRAM cell configuration and fabrication method 公开/授权日:2002-06-27
信息查询