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58 条记录 (耗时 0.019 秒)

    DRAM cell configuration and fabrication method
    1.
    发明授权
    DRAM cell configuration and fabrication method 有权

    公开(公告)号：US06504200B2

    公开(公告)日：2003-01-07

    申请号：US09951243

    申请日：2001-09-12

    申请人： Till Schlösser ,  Bernhard Sell ,  Josef Willer

    发明人： Till Schlösser ,  Bernhard Sell ,  Josef Willer

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

    摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

    Memory cell arrangement
    3.
    发明授权
    Memory cell arrangement 失效
    存储单元布置

    公开(公告)号：US06627940B1

    公开(公告)日：2003-09-30

    申请号：US09937838

    申请日：2002-02-05

    申请人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

    发明人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

    摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

    摘要翻译： 存储单元阵列包括形成平行的第一和第二沟槽的衬底。 晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。 与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。 相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。 在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。 绝缘空间横向与字线连接。 导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

    Integrated circuit configuration with at least one capacitor and method for producing the same
    4.
    发明授权
    Integrated circuit configuration with at least one capacitor and method for producing the same 有权
    具有至少一个电容器的集成电路配置及其制造方法

    公开(公告)号：US06525363B1

    公开(公告)日：2003-02-25

    申请号：US09677433

    申请日：2000-10-02

    申请人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

    发明人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

    IPC分类号： H01L27108

    CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/86 ,  H01L28/90

    摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

    摘要翻译： 设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。 横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。 横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻 相对于第二材料选择性地到达第一深度。 第一电容器电极设置有电容器电介质（KD）。 第二电容器电极（P）与电容器电介质（KD）相邻。

    Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors
    5.
    发明授权
    Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors 失效
    集成电路结构和制造具有掩埋位线或沟槽电容器的电容结构的方法

    公开(公告)号：US06800898B2

    公开(公告)日：2004-10-05

    申请号：US09951239

    申请日：2001-09-12

    申请人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

    发明人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

    IPC分类号： H01L2976

    CPC分类号： H01L27/10844 ,  H01L27/10861 ,  H01L27/10876

    摘要： The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

    摘要翻译： 形成在基板中的凹部的下部的底部和侧面具有绝缘结构。 第一导电类型的导电结构的第一部分位于凹部的下部。 低于第一类型的第二导电类型的导电结构的第二部分位于上部并且在凹部的侧面与基板的区域相邻。 导电结构在其第一和第二部分之间具有扩散阻挡层。 导电结构被配置为具有垂直晶体管的DRAM单元配置的位线，由此S / Du表示下源极/漏极区域，S / Do表示连接到存储电容器的上部源极/漏极区域。 或者，导电结构被配置为存储电容器，并且上部源极漏极/区域连接到位线。

    Metal gate structures with recessed channel
    8.
    发明授权
    Metal gate structures with recessed channel 有权
    带凹槽的金属门结构

    公开(公告)号：US07943992B2

    公开(公告)日：2011-05-17

    申请号：US12157556

    申请日：2008-06-10

    申请人： Bernhard Sell ,  Rishabh Mehandru

    发明人： Bernhard Sell ,  Rishabh Mehandru

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7834 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621

    摘要： Methods and associated structures of forming a microelectronic device are described. Those structures may comprise a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

    摘要翻译： 描述形成微电子器件的方法和相关结构。 这些结构可以包括晶体管，其包括设置在基板上的栅极电介质上的金属栅极和与晶体管的沟道区域相邻设置的源极/漏极区域。 源极/漏极区域包括源极/漏极延伸部分，其包括顶点，其中沟道区域的顶表面与顶点基本上是平面的。

    Semiconductor device having self-aligned epitaxial source and drain extensions
    10.
    发明申请
    Semiconductor device having self-aligned epitaxial source and drain extensions 有权
    具有自对准外延源极和漏极延伸部分的半导体器件

    公开(公告)号：US20080242037A1

    公开(公告)日：2008-10-02

    申请号：US11729189

    申请日：2007-03-28

    申请人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

    发明人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

    摘要翻译： 一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中 掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域 以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料 基质。