A random access memory (memory) includes one or more planes of memory arrays stacked on top of each other. Each plane may be manufactured separately, and each array within the plane may be enabled/disabled separately. In this manner, each memory array within the plane can be individually tested, and defective memory arrays may be sorted out, which increases the final yield and quality. A memory plane may be stacked on top of each other and on top of an active circuit plane to make a large capacity memory device. The memory may be volatile or non-volatile by using appropriate memory cells as base units. Also, the memory plane may be fabricated separately from the active circuitry. Thus the memory plane does not require a silicon substrate, and may be formed from a glass substrate for example. Further, each memory plane may be individually selected (or enabled) via plane memory select transistors. The array may be individually selected (or enable) via array select transistor. These transistors may be formed from amorphous silicon transistor(s) and/or thin-film transistor(s). The data bus, array select bus, and the plane select bus provide electrical connections between the memory planes and the active circuit plane via side contact pads on each plane. 3-D memory for large storage capacity. The memory may be formed from one or more planes with each plane including one or more memory arrays. Each memory array of each plane may be separately enabled or disabled. The memory array may be formed on silicon or non-silicon based substrate. An active circuit plane may be shared among the memory arrays and planes to perform read and write functions.