中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

64 records (took 0.02 seconds)

    Triple sample sensing for magnetic random access memory (MRAM) with series diodes
    2.
    发明授权
    Triple sample sensing for magnetic random access memory (MRAM) with series diodes 有权
    具有串联二极管的磁性随机存取存储器（MRAM）的三次采样检测

    公开(公告)号：US06873544B2

    公开(公告)日：2005-03-29

    申请号：US10696826

    申请日：2003-10-30

    Applicant: Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

    Inventor： Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

    CPC classification number: G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C27/02 ,  G11C2013/0057

    Abstract: A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.

    Abstract translation: 一种包括电阻式存储单元阵列的数据存储装置。 电阻存储单元可以包括磁性隧道结（MTJ）和薄膜二极管。 该装置可以包括电连接到阵列的电路，并且还能够监测流过所选择的存储器单元的信号电流。 一旦已经监视了信号电流，电路就可以将信号电流与平均参考电流进行比较，以确定所选择的存储单元处于第一电阻状态和第二电阻状态。另外，一种操作方法 数据存储设备。

    Method and system for performing equipotential sensing across a memory array to eliminate leakage currents
    6.
    发明授权
    Method and system for performing equipotential sensing across a memory array to eliminate leakage currents 有权

    公开(公告)号：US06678189B2

    公开(公告)日：2004-01-13

    申请号：US10084111

    申请日：2002-02-25

    Applicant: Lung T. Tran

    Inventor： Lung T. Tran

    IPC: G11C1115

    CPC classification number: G11C11/16

    Abstract: A method and system for minimizing a leaked current within an array of memory cells as well as a method and system for differentiating a resistive value within a sensed memory cell during a read operation are disclosed. The memory array includes a plurality of bit lines and word lines that are cross-coupled via a plurality of memory cells. Each memory cell is limited in providing a conductive path in a first direction only by way of a unidirectional element. Such unidirectional elements typically comprise of diodes. The apparatus utilizes the diodes to form a current path from the bit line to the word line having passed through the diode and resistive memory cell. Further, a differential sense amplifier is utilized to differentiate the sensed current during a read operation from a reference value after an equipotential value is placed across the array to limit leakage current from developing within adjoining word and bit lines during a sense operation of a given memory cell.

    3-D memory device for large storage capacity
    7.
    发明授权
    3-D memory device for large storage capacity 有权
    3-D存储设备，存储容量大

    公开(公告)号：US06504742B1

    公开(公告)日：2003-01-07

    申请号：US09984934

    申请日：2001-10-31

    Applicant: Lung T. Tran ,  Thomas C. Anthony

    Inventor： Lung T. Tran ,  Thomas C. Anthony

    IPC: G11C502

    CPC classification number: H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A random access memory (memory) includes one or more planes of memory arrays stacked on top of each other. Each plane may be manufactured separately, and each array within the plane may be enabled/disabled separately. In this manner, each memory array within the plane can be individually tested, and defective memory arrays may be sorted out, which increases the final yield and quality. A memory plane may be stacked on top of each other and on top of an active circuit plane to make a large capacity memory device. The memory may be volatile or non-volatile by using appropriate memory cells as base units. Also, the memory plane may be fabricated separately from the active circuitry. Thus the memory plane does not require a silicon substrate, and may be formed from a glass substrate for example. Further, each memory plane may be individually selected (or enabled) via plane memory select transistors. The array may be individually selected (or enable) via array select transistor. These transistors may be formed from amorphous silicon transistor(s) and/or thin-film transistor(s). The data bus, array select bus, and the plane select bus provide electrical connections between the memory planes and the active circuit plane via side contact pads on each plane. 3-D memory for large storage capacity. The memory may be formed from one or more planes with each plane including one or more memory arrays. Each memory array of each plane may be separately enabled or disabled. The memory array may be formed on silicon or non-silicon based substrate. An active circuit plane may be shared among the memory arrays and planes to perform read and write functions.

    Abstract translation: 随机存取存储器（存储器）包括堆叠在彼此之上的一个或多个存储器阵列平面。 每个平面可以单独制造，并且平面内的每个阵列可以单独启用/禁用。 以这种方式，可以单独地测试平面内的每个存储器阵列，并且可以整理出有缺陷的存储器阵列，这增加了最终的产量和质量。 存储器平面可以堆叠在彼此的顶部并且在有源电路平面的顶部上以形成大容量存储器件。 通过使用适当的存储器单元作为基本单元，存储器可以是易失性的或非易失性的。 此外，存储器平面可以与有源电路分开制造。 因此，存储器平面不需要硅衬底，并且可以由例如玻璃衬底形成。 此外，每个存储器平面可以经由平面存储器选择晶体管单独选择（或使能）。 阵列可以通过阵列选择晶体管单独选择（或使能）。 这些晶体管可以由非晶硅晶体管和/或薄膜晶体管形成。 数据总线，阵列选择总线和平面选择总线通过每个平面上的侧接触垫在存储器平面和有源电路平面之间提供电连接。 3-D内存大容量存储。 存储器可以由一个或多个平面形成，每个平面包括一个或多个存储器阵列。 每个平面的每个存储器阵列可以单独启用或禁用。 存储器阵列可以形成在硅或非硅基衬底上。 可以在存储器阵列和平面之间共享有源电路平面以执行读取和写入功能。

    Memory device having memory cells capable of four states
    8.
    发明授权
    Memory device having memory cells capable of four states 有权
    具有能够具有四种状态的存储单元的存储器件

    公开(公告)号：US06483734B1

    公开(公告)日：2002-11-19

    申请号：US09992426

    申请日：2001-11-26

    Applicant: Manish Sharma ,  Lung T. Tran

    Inventor： Manish Sharma ,  Lung T. Tran

    IPC: G11C1702

    CPC classification number: H01L27/224 ,  G11C11/005 ,  G11C11/16 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5671 ,  G11C17/16 ,  G11C2216/26

    Abstract: A memory device includes memory cells having a re-writeable element and a write-once element in series with the re-writeable element. The re-writeable element is programmable between a high resistance state and a low resistance state. The write-once element can be an anti-fuse element that is programmable from a high resistance state to a low resistance state, or a fuse element that is programmable from a low resistance state to a high resistance state. The two possible states for the re-writeable element and the two possible states for the write-once element allow the memory cells to store four different bits.

    Abstract translation: 存储器件包括具有可重写元件和与可重写元件串联的一次写入元件的存储器单元。 可重写元件可在高电阻状态和低电阻状态之间编程。 一次写入元件可以是可从高电阻状态到低电阻状态的可编程熔丝元件，或可从低电阻状态到高电阻状态的可编程熔丝元件。 可重写元件的两种可能状态和一次写入元件的两种可能状态允许存储单元存储四个不同的位。

    MRAM device using magnetic field bias to improve reproducibility of memory cell switching
    9.
    发明授权
    MRAM device using magnetic field bias to improve reproducibility of memory cell switching 有权
    使用磁场偏置的MRAM器件提高存储器单元切换的再现性

    公开(公告)号：US6163477A

    公开(公告)日：2000-12-19

    申请号：US370087

    申请日：1999-08-06

    Applicant: Lung T. Tran

    Inventor： Lung T. Tran

    IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    CPC classification number: G11C11/15

    Abstract: A magnetic field bias is applied to memory cells of an MRAM device during a write operation. The magnetic field bias, which may be applied by a permanent magnet or an electromagnet, can improve reproducibility of memory cell switching.

    Abstract translation: 在写入操作期间，磁场偏置被施加到MRAM器件的存储单元。 可以由永磁体或电磁体施加的磁场偏置可以提高存储器单元切换的再现性。

    Increased magnetic memory array sizes and operating margins
    10.
    发明授权
    Increased magnetic memory array sizes and operating margins 有权
    增加磁存储器阵列大小和运行裕度

    公开(公告)号：US07376004B2

    公开(公告)日：2008-05-20

    申请号：US10661448

    申请日：2003-09-11

    Applicant: James R. Eaton, Jr. ,  Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

    Inventor： James R. Eaton, Jr. ,  Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

    IPC: G11C11/00 ,  G11C11/14

    CPC classification number: G11C11/16

    Abstract: A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.

    Abstract translation: 用于制造磁随机存取存储器（MRAM）的方法在操作期间隔离MRAM阵列中的每个存储单元直到被选择。 一些实施例使用用于这种电隔离的串联连接的二极管。 只有选定的一个存储器单元将在相应的位和字线之间传导电流。 读取和写入数据访问电流的更好，更均匀的分布会导致所有存储单元。 在另一个实施例中，该改进用于增加支持较大数据阵列的行数和列数。 在另一实施例中，这种改进用于增加操作裕度并减少必要的数据写入电压和电流。

Patent Agency Ranking