A semiconductor memory device comprises first and second pins, a controller, a first command decoder and a lower-side command decoder. The controller is supplied with a signal indicating that a read command is input and a signal indicating that a write command is input based on the signal input to the first pin. The first command decoder is controlled by an output signal of the controller, defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via the second pin and decodes the first command. A lower-side command decoder is controlled by an output signal of the controller, fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command, and outputs a lower address latch command, mode register set command and auto-refresh command.