发明授权
- 专利标题： Combined floating-point logic core and frame buffer
- 专利标题（中）： 组合浮点逻辑核心和帧缓冲区
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申请号： US09294546申请日： 1999-04-19
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公开(公告)号： US06532018B1公开(公告)日： 2003-03-11
- 发明人: Edward C. Chen , Mark S. Grossman , Chi-Shung Wang , John S. Montrym , Mark M. Leather
- 申请人： Edward C. Chen , Mark S. Grossman , Chi-Shung Wang , John S. Montrym , Mark M. Leather
- 主分类号： G06F1314
- IPC分类号： G06F1314
摘要：
A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.
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