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公开(公告)号：US06760033B2
公开(公告)日：2004-07-06
申请号：US10264524
申请日：2002-10-04
IPC分类号： G06F1314
CPC分类号： G06T15/005
摘要： A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.
摘要翻译： 一种用于图形处理的方法和装置。 执行像素片段处理和处理的逻辑核心在具有一个或多个存储器单元的单个衬底上被实例化。 存储器单元可动态地分段为帧缓冲器和纹理存储器。 由于逻辑核心与存储器单元在同一基板上，因此核心和存储器之间的带宽大大增加。
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公开(公告)号：US06532018B1
公开(公告)日：2003-03-11
申请号：US09294546
申请日：1999-04-19
IPC分类号： G06F1314
CPC分类号： G06T15/005
摘要： A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.
摘要翻译： 一种用于图形处理的方法和装置。 执行像素片段处理和处理的逻辑核心在具有一个或多个存储器单元的单个衬底上被实例化。 存储器单元可动态地分段为帧缓冲器和纹理存储器。 由于逻辑核心与存储器单元在同一基板上，因此核心和存储器之间的带宽大大增加。
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公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译： 为分级处理器提供了设备和方法。 所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件 与不同阶段的图形处理相关联的多类图形操作。 处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的 来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。
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公开(公告)号：US20120026171A1
公开(公告)日：2012-02-02
申请号：US13269462
申请日：2011-10-07
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译： 用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。 耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。
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5.发明授权Graphics system with virtual memory pages and non-power of two number of memory elements 有权图形系统具有虚拟内存页面和非功能两个内存元素公开(公告)号：US08072463B1
公开(公告)日：2011-12-06
申请号：US11538755
申请日：2006-10-04
CPC分类号： G06F12/0607 , G06F12/10
摘要： A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. Additionally, a partition swizzling operation is used to adjust the partition numbers associated with individual units of virtual memory allocation on particular virtual memory pages to achieve a selected partition interleaving pattern.
摘要翻译： 图形系统利用虚拟存储器页面并具有包括存储器元件的分区图形存储器。 该系统支持具有两个非活动存储器元件的非功率。 此外，使用分区旋转操作来调整与特定虚拟存储器页面上的虚拟存储器分配的单独单元相关联的分区号，以实现所选择的分区交织模式。
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公开(公告)号：US20100106921A1
公开(公告)日：2010-04-29
申请号：US12650068
申请日：2009-12-30
申请人： David B. Glasco , John S. Montrym , Lingfeng Yuan
发明人： David B. Glasco , John S. Montrym , Lingfeng Yuan
CPC分类号： G06F12/10 , G06F12/1027 , G06F2212/302 , G06F2212/681 , G06F2212/684
摘要： A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.
摘要翻译： 描述共享存储器管理系统和方法。 在一个实施例中，存储器管理系统包括用于同时管理来自多个引擎的存储器访问请求的存储器管理单元。 共享内存管理系统独立控制对上下文内存的访问，而不受其他引擎活动的干扰。 在一个示例性实现中，存储器管理单元跟踪构成存储器访问请求的多个引擎中的每一个的标识符。 存储器管理单元分别将多个引擎中的每一个与特定的翻译信息相关联。 该翻译信息由块绑定操作指定。 在一个实施例中，翻译信息存储在实例存储器的一部分中。 存储器管理单元可以是非阻塞的，并且还可以允许命中。
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公开(公告)号：US07681077B1
公开(公告)日：2010-03-16
申请号：US11556630
申请日：2006-11-03
IPC分类号： G06F11/00
CPC分类号： G06F11/3692 , G06F11/3648
摘要： A graphics processing unit has a reduced memory space shadow memory as a source of state information for performing validation of commands. The reduced memory space shadow memory is smaller in size than a full version of state variables associated with an abstract state machine representation of a class of commands received from a software driver.
摘要翻译： 图形处理单元具有减小的存储空间影子存储器作为用于执行命令验证的状态信息源。 缩小的内存空间影子内存的大小要比与从软件驱动程序接收的一组命令的抽象状态机表示相关联的状态变量的完整版本小。
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8.发明授权公开(公告)号：US07081902B1
公开(公告)日：2006-07-25
申请号：US10671237
申请日：2003-09-24
IPC分类号： G09G5/00
CPC分类号： G09G5/363 , G09G2320/0276 , G09G2320/0673
摘要： A graphics processor performed gamma correction of the coverage values of pixels. In one embodiment, a gamma correction factor is written into a run-time loadable lookup table of the graphics processor. The gamma corrected coverage values may be used in an anti-aliasing process to form smoothed primitives.
摘要翻译： 图形处理器对像素的覆盖值进行伽马校正。 在一个实施例中，将伽马校正因子写入图形处理器的运行时可加载查找表中。 伽马校正的覆盖值可以用于抗锯齿过程以形成平滑的原语。
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公开(公告)号：US07053901B2
公开(公告)日：2006-05-30
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
发明人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译： 本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU，或者管理专用处理器的驱动器。 有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。 可以基于性能考虑，有选择地使用协处理器。
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公开(公告)号：US06992669B2
公开(公告)日：2006-01-31
申请号：US10198707
申请日：2002-07-17
IPC分类号： G06T17/00
CPC分类号： G06T11/40 , G06T15/005 , G06T15/04 , G06T15/50 , G06T15/503 , G06T15/506
摘要： A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the graphics data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data received from the lighting module. During use, an antialiasing feature is implemented on the single semiconductor platform to improve a quality of the graphics rendering.
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