- 专利标题: High speed semiconductor memory device with short word line switching time
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申请号: US10034076申请日: 2002-01-03
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公开(公告)号: US06538933B2公开(公告)日: 2003-03-25
- 发明人: Takashi Akioka , Masao Shinozaki
- 申请人: Takashi Akioka , Masao Shinozaki
- 优先权: JP11-278285 19990930
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
Setting means (such as fuse circuits) for adjusting the timings of various signals such as an activation timing of a sense amplifier, a fall timing of a word line, a recovery operation (equalization) of a bit lines and so forth, checking an operation in a test stage of a chip, and permanently programming (fixing) the timing of an internal signal to the condition of the highest operation speed that can be confirmed as acquirable in this check stage, is provided.
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