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公开(公告)号:US07254068B2
公开(公告)日:2007-08-07
申请号:US11375060
申请日:2006-03-15
IPC分类号: G11C7/00
CPC分类号: G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译: 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形,另一个的另一个的部分的中心和第二全局位线的截面的中心位于这些 互补位线是一个等腰三角形。
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公开(公告)号:US20050128839A1
公开(公告)日:2005-06-16
申请号:US11046690
申请日:2005-02-01
IPC分类号: G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号: G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号:US06856559B2
公开(公告)日:2005-02-15
申请号:US10637549
申请日:2003-08-11
IPC分类号: G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号: G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译: 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形,另一个的另一个的部分的中心和第二全局位线的部分的直线布置在其上方 互补位线是一个等腰三角形。
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公开(公告)号:US06625070B2
公开(公告)日:2003-09-23
申请号:US10011488
申请日:2001-12-11
IPC分类号: G11C700
CPC分类号: G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号:US20060158918A1
公开(公告)日:2006-07-20
申请号:US11375060
申请日:2006-03-15
IPC分类号: G11C5/06
CPC分类号: G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号:US07808107B2
公开(公告)日:2010-10-05
申请号:US12453383
申请日:2009-05-08
申请人: Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人: Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号: H01L23/48
CPC分类号: H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
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7.
公开(公告)号:US06770941B2
公开(公告)日:2004-08-03
申请号:US10002009
申请日:2001-12-05
申请人: Masao Shinozaki , Takashi Akioka , Kinya Mitsumoto
发明人: Masao Shinozaki , Takashi Akioka , Kinya Mitsumoto
IPC分类号: H01L2976
CPC分类号: H01L27/088 , H01L21/823412 , H01L21/823456 , H01L21/823462
摘要: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.
摘要翻译: 本发明提供一种在不增加芯片尺寸和生产成本的情况下制造符合多种电源电压规格的半导体器件的方法,同时器件实现高速性能。 该方法包括多个处理,用于形成与外部电源电压相对应地供应不同电源电压的多种类型的MOS晶体管,这些外部电源电压由多种类型的MOS晶体管共同的第一种处理,第一种处理之后的第二种处理, 这是多种类型的MOS晶体管中的每一种不同的,以及第二种处理之后的第三种处理,这对于多种类型的MOS晶体管是共同的。
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公开(公告)号:US06538933B2
公开(公告)日:2003-03-25
申请号:US10034076
申请日:2002-01-03
申请人: Takashi Akioka , Masao Shinozaki
发明人: Takashi Akioka , Masao Shinozaki
IPC分类号: G11C700
CPC分类号: G11C7/22 , G11C7/1072 , G11C8/08 , G11C11/413 , G11C2207/2281
摘要: Setting means (such as fuse circuits) for adjusting the timings of various signals such as an activation timing of a sense amplifier, a fall timing of a word line, a recovery operation (equalization) of a bit lines and so forth, checking an operation in a test stage of a chip, and permanently programming (fixing) the timing of an internal signal to the condition of the highest operation speed that can be confirmed as acquirable in this check stage, is provided.
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公开(公告)号:US07982314B2
公开(公告)日:2011-07-19
申请号:US12805261
申请日:2010-07-21
申请人: Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人: Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号: H01L23/48
CPC分类号: H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
摘要翻译: 构成电路的电路元件和布线以及与这种电路电连接的第一电极设置在半导体衬底的一个主表面上。 除了第一电极的表面上的开口之外,在电路上形成有机绝缘膜。 第一和第二外部连接电极设置在有机绝缘膜上。 用于将第一和第二外部连接电极和第一电极电连接的至少一个导电层被放置在有机绝缘膜上。
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公开(公告)号:US20100308458A1
公开(公告)日:2010-12-09
申请号:US12805261
申请日:2010-07-21
申请人: Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
发明人: Masao Shinozaki , Kenji Nishimoto , Takashi Akioka , Yutaka Kohara , Sanae Asari , Shusaku Miyata , Shinji Nakazato
IPC分类号: H01L23/498
CPC分类号: H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01027
摘要: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
摘要翻译: 构成电路的电路元件和布线以及与这种电路电连接的第一电极设置在半导体衬底的一个主表面上。 除了第一电极的表面上的开口之外,在电路上形成有机绝缘膜。 第一和第二外部连接电极设置在有机绝缘膜上。 用于将第一和第二外部连接电极和第一电极电连接的至少一个导电层被放置在有机绝缘膜上。
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