Methods and arrangements are provided for use in memory devices, which allow column address strobe (CAS) timing to adjust to, and/or be adjusted by a controller to, have both minimal unloaded latency and optimal pipelined latency. A delay CAS (DC) period is only applied until a row-to-column delay (tRCD) has been satisfied. Once the tRCD has been satisfied, then the DC period is not enforced for subsequent CAS operations within the memory core associated with a page hit. When a subsequent read command is received at the input/output pins of the memory device and a corresponding RAS operation is performed in the memory core, then the tRCD will again need to be satisfied and a DC period will again be enforced. Consequently the methods and arrangements allow the CAS delay to be dynamically and selectively adjusted to best support the workload. This results in better performance and increased bandwidth.