发明授权
- 专利标题： Efficient data compression circuit for memory testing
- 专利标题（中）： 高效数据压缩电路，用于内存测试
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申请号： US09336785申请日： 1999-06-21
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公开(公告)号： US06543015B1公开(公告)日： 2003-04-01
- 发明人: Gyh-Bin Wang , Der-Min Yuan
- 申请人： Gyh-Bin Wang , Der-Min Yuan
- 主分类号： G06F1100
- IPC分类号： G06F1100
摘要：
In this invention two compression circuits are combined to produce at a single output pass/fail condition for a plurality of memory addresses and a plurality of I/O. The output of an address compression circuit is connected to an I/O circuit. An I/O compression circuit is connected to several I/O circuits and the output of the I/O compression circuit controls a selected data output driver to provide a combined test result of the plurality of addresses and the plurality of I/O. The combination of the two compression circuits is made possible because the address data compression circuits and the I/O compression circuits use different truth tables.
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