发明授权
US06548871B1 Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer
失效
半导体器件通过在相同的线层中形成第一层布线和栅极上电极来实现缩短的布线长度并减少布线延迟
- 专利标题： Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer
- 专利标题（中）： 半导体器件通过在相同的线层中形成第一层布线和栅极上电极来实现缩短的布线长度并减少布线延迟
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申请号： US09543349申请日： 2000-04-05
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公开(公告)号： US06548871B1公开(公告)日： 2003-04-15
- 发明人: Katsuyuki Horita , Takashi Kuroi , Yasuyoshi Itoh , Katsuomi Shiozawa
- 申请人： Katsuyuki Horita , Takashi Kuroi , Yasuyoshi Itoh , Katsuomi Shiozawa
- 优先权： JP11-305108 19991027
- 主分类号： H01L2976
- IPC分类号： H01L2976
摘要：
Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
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