发明授权
US06549466B1 Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物(ONO)结构的非易失性存储单元的擦除时间

  • 专利标题: Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
  • 专利标题(中): 使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物(ONO)结构的非易失性存储单元的擦除时间
  • 申请号: US09657143
    申请日: 2000-09-07
  • 公开(公告)号: US06549466B1
    公开(公告)日: 2003-04-15
  • 发明人: Narbeh DerhacobianMichael Van BuskirkChi ChangDaniel Sobek
  • 申请人: Narbeh DerhacobianMichael Van BuskirkChi ChangDaniel Sobek
  • 主分类号: G11C1604
  • IPC分类号: G11C1604
Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
摘要:
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.
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