Invention Grant
- Patent Title: Synchronous semiconductor device, and inspection system and method for the same
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Application No.: US09820715Application Date: 2001-03-30
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Publication No.: US06559669B2Publication Date: 2003-05-06
- Inventor: Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Tanaka
- Applicant: Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Tanaka
- Priority: JP2000-365053 20001130
- Main IPC: G01R3128
- IPC: G01R3128

Abstract:
The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
Public/Granted literature
- US20020066058A1 Synchronous semiconductor device, and inspection system and method for the same Public/Granted day:2002-05-30
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