Invention Grant
US06560755B1 Apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits
失效
用于建模和模拟集成电路设计流程中不匹配影响的装置和方法
- Patent Title: Apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits
- Patent Title (中): 用于建模和模拟集成电路设计流程中不匹配影响的装置和方法
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Application No.: US09648396Application Date: 2000-08-24
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Publication No.: US06560755B1Publication Date: 2003-05-06
- Inventor: Xisheng Zhang , James Chieh-Tsung Chen , Zhihong Liu , Jushan Xie , Xucheng Pang , Jingkun Fang
- Applicant: Xisheng Zhang , James Chieh-Tsung Chen , Zhihong Liu , Jushan Xie , Xucheng Pang , Jingkun Fang
- Main IPC: G06F1750
- IPC: G06F1750

Abstract:
An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on said mismatch values, and extracting said mismatch model based on said set of linking coefficients. In another embodiment, the attaching of the mismatch model to the netlist includes determining a number of layers in the netlist, generating a copy of a lower layer in the netlist, the copy including a reference to a mismatch model definition, generating a copy of a higher layer in the netlist, replacing a reference to the lower layer in the higher layer by a reference to the copy of the lower layer, and generating a new model definition.
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