发明授权
- 专利标题： Integrated circuits with reduced substrate capacitance
- 专利标题（中）： 具有降低衬底电容的集成电路
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申请号： US09702314申请日： 2000-10-31
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公开(公告)号： US06562666B1公开(公告)日： 2003-05-13
- 发明人: Heemyong Park , Fariborz Assaderaghi , Jack A. Mandelman , Ghavam G. Shahidi , Lawrence F. Wagner, Jr.
- 申请人： Heemyong Park , Fariborz Assaderaghi , Jack A. Mandelman , Ghavam G. Shahidi , Lawrence F. Wagner, Jr.
- 主分类号： H01L2100
- IPC分类号： H01L2100
摘要：
Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.