公开(公告)号：US06835983B2

公开(公告)日：2004-12-28

申请号：US10280661

申请日：2002-10-25

Applicant: Tak H. Ning ,  Devendra K. Sadana

Inventor： Tak H. Ning ,  Devendra K. Sadana

IPC: H01L2100

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract translation: 本发明提供SOI材料，其包括具有不同厚度的区域的顶部含Si层以及制造这种SOI材料的方法。 本发明的方法包括通过硅的掩蔽氧化来稀释顶部含Si层的预定区域的步骤。 还公开了包括具有不同类型的CMOS器件的本发明SOI材料的SOI IC芯片。

公开(公告)号：US06835606B2

公开(公告)日：2004-12-28

申请号：US10604858

申请日：2003-08-22

Applicant: Chia-Tien Peng ,  Huan-Chao Wu

Inventor： Chia-Tien Peng ,  Huan-Chao Wu

IPC: H01L2100

CPC classification number: H01L29/04 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/1281 ,  H01L29/78621 ,  H01L29/78675

Abstract: A low temperature polysilicon thin film transistor and a method of forming the polysilicon layer inside the thin film transistor. An amorphous silicon layer is formed over a panel. The panel has a display region and a peripheral circuit region. A metallic layer is formed over a portion of the amorphous silicon layer in the peripheral circuit region. A crystallization process is performed to transform the amorphous silicon layer in the peripheral circuit region into a polysilicon layer. Thereafter, an excimer laser annealing process is performed to increase the grain size of the polysilicon layer in the peripheral circuit region and, at the same time, transform the amorphous silicon layer in the display region into a polysilicon layer. Since the average grain size of the polysilicon layer in the peripheral circuit region is larger, electron mobility is increased as demanded. Similarly, since the average grain size of the polysilicon layer in the display region is smaller, leakage current is decreased as demanded.

Abstract translation: 低温多晶硅薄膜晶体管和在薄膜晶体管内部形成多晶硅层的方法。 在面板上形成非晶硅层。 面板具有显示区域和外围电路区域。 在外围电路区域中的非晶硅层的一部分上形成金属层。 进行结晶处理以将外围电路区域中的非晶硅层转变为多晶硅层。 此后，进行准分子激光退火处理以增加外围电路区域中的多晶硅层的晶粒尺寸，同时将显示区域中的非晶硅层转变为多晶硅层。 由于外围电路区域中的多晶硅层的平均晶粒尺寸较大，所以电子迁移率根据需要增加。 类似地，由于显示区域中的多晶硅层的平均晶粒尺寸较小，所以泄漏电流按要求减小。

公开(公告)号：US06835586B2

公开(公告)日：2004-12-28

申请号：US09837558

申请日：2001-04-19

Applicant: Shunpei Yamazaki ,  Hisashi Ohtani

Inventor： Shunpei Yamazaki ,  Hisashi Ohtani

IPC: H01L2100

CPC classification number: H01L27/1255 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648

Abstract: Providing a semiconductor device with a TFT structure with high reliability In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 107a is provided in an n-channel TFT. The LDD regions 113 overlaps the first wiring line 102a and does not overlap the second wiring line 107a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

Abstract translation: 提供具有高可靠性的TFT结构的半导体器件在基板100上形成的CMOS电路中，在n型栅极配线中设置有从属栅极布线（第1布线）102a和主栅极布线（第2布线） 通道TFT。 LDD区域113与第一布线102a重叠，不与第二布线107a重叠。 因此，向第一布线施加栅极电压形成GOLD结构，而不施加形成LLD结构。 以这种方式，可以根据电路所需的相应规格适当地使用GOLD结构和LLD结构。

公开(公告)号：US06835582B1

公开(公告)日：2004-12-28

申请号：US10342656

申请日：2003-01-15

Applicant: Michael A. Deeds ,  Kevin Cochran

Inventor： Michael A. Deeds ,  Kevin Cochran

IPC: H01L2100

CPC classification number: G02B6/3636 ,  G02B6/3692

Abstract: A method of sealing an optical fiber in a microchip includes providing a device microchip, a top microchip and an optical fiber; forming a groove in at least one of the device microchip and the top microchip; coating metal on the optical fiber; depositing metal on the groove and top surfaces of the device microchip and the top microchip; depositing solder on the top surface of at least one of the device microchip and the top microchip; placing the optical fiber in the groove; placing the top microchip on the device microchip; and reflowing the solder to form a hermetic seal.

Abstract translation: 密封微芯片中的光纤的方法包括提供器件微芯片，顶部微芯片和光纤; 在装置微芯片和顶部微芯片中的至少一个中形成凹槽; 在光纤上涂上金属; 将金属沉积在器件微芯片和顶部微芯片的凹槽和顶表面上; 在装置微芯片和顶部微芯片中的至少一个的顶表面上沉积焊料; 将光纤放置在槽中; 将顶部微芯片放置在器件微芯片上; 并回流焊料以形成气密封。

公开(公告)号：US06835575B2

公开(公告)日：2004-12-28

申请号：US10402642

申请日：2003-03-28

Applicant: Yong Chen

Inventor： Yong Chen

IPC: H01L2100

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/77 ,  H01L21/76823 ,  H01L21/76834 ,  H01L21/76888 ,  H01L27/28 ,  H01L51/0595

Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a passivation layer is provided to protect a molecular layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.

Abstract translation: 描述了在加工期间制造保持电子器件的有源分子层的完整性的分子电子器件的工艺。 在一个方面，提供钝化层以保护分子层免受顶层线图案化期间的退化。 描述由该制造工艺形成的分子电子器件结构和存储器系统。

公开(公告)号：US06833282B2

公开(公告)日：2004-12-21

申请号：US10435043

申请日：2003-05-12

Applicant: Robert Groulx ,  Raymond Frost ,  Yves Tremblay

Inventor： Robert Groulx ,  Raymond Frost ,  Yves Tremblay

IPC: H01L2100

CPC classification number: H01L21/32051 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/53257 ,  H01L27/14812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to make a charge couple device including an interconnect layer to contact active areas, a first layer of a first titanium nitride layer on the active areas, and then a series of alternating titanium and titanium nitride layers are deposited to form a composite sandwich structure. This structure is less prone flaking while able to withstand high temperature treatment during fabrication of backside illuminated sensors to improve quantum efficiency and reduce dark current.

Abstract translation: 为了使包括互连层的电荷耦合器件接触有源区域，在有源区域上的第一氮化钛层的第一层，然后沉积一系列交替的钛和氮化钛层以形成复合夹层结构 。 这种结构较不容易剥落，同时能够在制造背面照明传感器的过程中承受高温处理，以提高量子效率和减少暗电流。

公开(公告)号：US06833079B1

公开(公告)日：2004-12-21

申请号：US09506425

申请日：2000-02-17

Applicant: Sara Giordani

Inventor： Sara Giordani

IPC: H01L2100

CPC classification number: H01L21/32137 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The present disclosure pertains to our discovery of a method of etching a shaped cavity in a substrate, where the shaped cavity has a width that is at least as great as its depth. We have discovered that by varying the process chamber pressure during etching of the shaped cavity, we can control lateral etching of the shaped cavity, while allowing the removal of etch process byproducts from the shaped cavity during continued etching. The method of the invention can be used to etch shaped cavities having round or horizontal elliptical shapes. The method of the invention is particularly useful in the etching of buried cavities, where removal of etch byproducts from the cavity can be difficult.

Abstract translation: 本公开涉及我们发现蚀刻衬底中的成形腔的方法，其中成形腔的宽度至少与其深度一样大。 我们已经发现，通过在蚀刻成形腔体期间改变处理室压力，我们可以控制成型腔的横向蚀刻，同时允许在连续蚀刻期间从成形腔去除蚀刻工艺副产物。 本发明的方法可用于蚀刻具有圆形或水平椭圆形状的成形空腔。 本发明的方法在掩埋空腔的蚀刻中特别有用，其中难以从腔中去除蚀刻副产物。

公开(公告)号：US06830953B1

公开(公告)日：2004-12-14

申请号：US10245428

申请日：2002-09-17

Applicant: Chenming Hu ,  Yee-Chia Yeo

Inventor： Chenming Hu ,  Yee-Chia Yeo

IPC: H01L2100

CPC classification number: H01L29/78 ,  H01L29/49

Abstract: A method for forming a MOSFET having greatly reduced leakage current between the gate electrode and the channel, source and drain regions. The method requires the use of gate electrode materials having lower electron affinities than the channel, source and drain regions. Gate electrode materials with negative electron affinities will also achieve the objectives of the invention. The use of these gate electrode materials enables the band structures of the gate electrode and the other regions to be aligned in a manner that eliminates tunneling states for carriers tunneling between the gate and the body of the device.

Abstract translation: 一种用于形成MOSFET的方法，其在栅电极和沟道，源极和漏极区之间具有大大降低的漏电流。 该方法需要使用具有比沟道，源极和漏极区域更低的电子亲和力的栅电极材料。 具有负电子亲和力的栅电极材料也将实现本发明的目的。 使用这些栅极电极材料能够使栅电极和其它区域的带结构以排除隧道状态的方式排列，以便在器件的栅极和主体之间隧穿。

公开(公告)号：US06830947B2

公开(公告)日：2004-12-14

申请号：US09929675

申请日：2001-08-14

Applicant: Hiroyuki Kamiya ,  Shuhichi Odahara ,  Kohichi Toriumi ,  Toshiyuki Yokoue

Inventor： Hiroyuki Kamiya ,  Shuhichi Odahara ,  Kohichi Toriumi ,  Toshiyuki Yokoue

IPC: H01L2100

CPC classification number: G02F1/1303 ,  B32B17/06 ,  B32B17/10018 ,  B32B17/10706 ,  G02F1/1333 ,  G02F1/1341 ,  G02F1/1362 ,  G02F2001/133354 ,  G02F2001/13415

Abstract: A broad crystal display panel having a color filter substrate is supported by supporting nails and the middle portion of a supporting span is pressed by a loading bar. From this state, the supporting nails are removed to release the supporting, and subsequently the supporting nails are also removed to release the supporting the color filter substrate. While preventing the displacement between the color filter substrate and a TFT array substrate, the color filter substrate and the TFT array substrate can be stacked with a specified distance.

Abstract translation: 具有滤色器基板的宽晶体显示面板通过支撑指甲支撑，支撑跨距的中间部分被装载杆按压。 从该状态，移除支撑指甲以释放支撑物，随后也移除支撑指甲以释放支撑滤色器基板。 同时防止滤色器基板和TFT阵列基板之间的位移，滤色器基板和TFT阵列基板可以以特定的距离堆叠。

公开(公告)号：US06830652B1

公开(公告)日：2004-12-14

申请号：US09678741

申请日：2000-10-04

Applicant: Tadahiro Ohmi ,  Masaki Hirayama

Inventor： Tadahiro Ohmi ,  Masaki Hirayama

IPC: H01L2100

CPC classification number: C23C16/45565 ,  C23C16/24 ,  C23C16/345 ,  C23C16/45578 ,  C23C16/511 ,  H01J37/32192 ,  H01J37/3244

Abstract: In a microwave plasma processing apparatus, a metal made lattice-like shower plate 111 is provided between a dielectric material shower plate 103, and a plasma excitation gas mainly an inert gas and a process gas are discharged from different locations. High energy ions can be incident on a surface of the substrate 114 by grounding the lattice-like shower plate. The thickness of each of the dielectric material separation wall 102 and the dielectric material at a microwave introducing part is optimized so as to maximize the plasma excitation efficiency, and, at the same time, the distance between the slot antenna 110 and the dielectric material separation wall 102 and a thickness of the dielectric material shower plate 103 are optimized so as to be capable of supplying a microwave having a large power.

Abstract translation: 在微波等离子体处理装置中，在介电材料喷淋板103和主要是惰性气体的等离子体激发气体之间设置金属制的格子状喷淋板111，从不同的位置排出处理气体。 高能离子可以通过使网状淋浴板接地而入射在基板114的表面上。 优化了微波引入部分的电介质材料分离壁102和电介质材料中的每一个的厚度，以使等离子体激发效率最大化，并且同时，缝隙天线110与电介质材料分离之间的距离 电介质材料喷淋板103的厚度优化，能够供给具有大功率的微波。