Invention Grant
- Patent Title: Triple layer isolation for silicon microstructure and structures formed using the same
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Application No.: US09885832Application Date: 2001-06-19
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Publication No.: US06569702B2Publication Date: 2003-05-27
- Inventor: Dong-il Cho , Sangwoo Lee , Sangjun Park
- Applicant: Dong-il Cho , Sangwoo Lee , Sangjun Park
- Priority: KR2000-37659 20000703
- Main IPC: H01L2100
- IPC: H01L2100

Abstract:
An isolation method for a single crystalline silicon microstructure using a triple layer structure is disclosed. The method includes forming the triple layer composed of an insulation layer formed over an exposed surface of the silicon microstructure, a conductive layer formed over the entire insulation layer, and a metal layer formed over a top portion of the microstructure; and partially etching the conductive layer to form electrical isolation between parts of the microstructure. The method does not require a separate photolithography process for isolation, and can be effectively applied to microstructures having high aspect ratios and narrow trenches. Also disclosed are single crystalline silicon microstructures having a triple layer isolation structure formed using the disclosed method.
Public/Granted literature
- US20020001871A1 Triple layer isolation for silicon microstructure and structures formed using the same Public/Granted day:2002-01-03
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